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general description the max8796/MAX8797/max17401 are 1-phase quick- pwm? step-down vid power-supply controllers for intel notebook cpus and graphics. the quick-pwm control provides instantaneous response to fast load current steps. active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. the max8796/MAX8797/max17401 are intended for two different notebook cpu/gpu core applications: either bucking down the battery directly to create the core voltage, or else bucking down the +5v system supply. the single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. alternatively, 2-stage conversion (stepping down the +5v system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. a slew-rate controller allows controlled transitions between vid codes. a thermistor-based temperature sensor provides programmable thermal protection. a power monitor provides an analog voltage output pro- portional to the power consumed by the cpu/gpu. the max8796/max17401 implement both the intel imvp-6 cpu core specifications, as well as the intel gmch graphics core specifications. the MAX8797 implements the intel gmch graphics core specifica- tions. the max8796/max17401 are available in a 32- pin tqfn package. the MAX8797 is available in a 28-pin tqfn package. applications imvp-6/imvp-6+ core power supply intel gmch crestline/cantiga graphics core power supply voltage-positioned step-down converters 2 to 4 lithium-ion (li+) cell battery-to-cpu core supply converters notebooks/desktops/servers featur es 1-phase quick-pwm controller ?.5% v out accuracy over line, load, and temperature 7-bit imvp-6 dac (max8796/max17401 only) 5-bit gmch dac active voltage positioning with adjustable gain accurate droop and current limit remote output and ground sense adjustable output-voltage slew rate power-good window comparator power monitor temperature comparator drives large synchronous rectifier fets 2v to 26v power input range adjustable switching frequency (600khz max) output overvoltage protection (max8796/ MAX8797 only) undervoltage and thermal-fault protection soft-startup and soft-shutdown internal boost diodes max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ________________________________________________________________ maxim integrated products 1 max8796 max17401 thin qfn 5mm x 5mm top view pad gnd 29 30 28 27 12 11 13 gnds csn csp dprstp dprslpvr 14 pwr v dd pgnd d6 bst d5 (stdby) d4 12 vrhot 4567 23 24 22 20 19 18 time ilim d0 v3p3 (gmch) clken shdn fb dl 3 21 31 10 v cc pwrgd 32 9 ccv ton pgdin 26 15 d1 dh 25 16 d2 thrm d3 8 17 lx pin configurations ordering information 19-2452; rev 1; 8/08 for information on other maxim products, visit maxim? website at www.maxim-ic.com. confidential informa tion?estricted to intel imvp-6 licensees evaluation kit available + denotes a lead-free/rohs-compliant package. part temp range pin-package feature max8796 gtj+ -40 o c to +105 o c 32 tqfn imvp-6/gmch MAX8797 gti+ -40 o c to +105 o c 28 tqfn gmch only max17401 gtj+ -40 o c to +105 o c 32 tqfn imvp-6/gmch pin configurations continued at end of data sheet. quick-pwm is a trademark of maxim integrated products, inc. http://
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 2 _______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees absolute maximum ratings electrical characteristics (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v dd to gnd .....................................................-0.3v to +6v csp, csn to gnd ....................................................-0.3v to +6v ilim, thrm, dprslpvr, vrhot , pwrgd to gnd ...................................................-0.3v to +6v ccv, fb, pwr, time to gnd .....................-0.3v to (v cc + 0.3v) shdn to gnd (note 1) ...........................................-0.3v to +30v ton to gnd ...........................................................-0.3v to +30v gnds, pgnd to gnd ...........................................-0.3v to +0.3v dl to pgnd ................................................-0.3v to (v dd + 0.3v) bst to gnd ............................................................-0.3v to +36v lx to bst ..................................................................-6v to +0.3v bst to v dd .............................................................-0.3v to +30v dh to lx ....................................................-0.3v to (v bst + 0.3v) max8796/max17401 only: v3p3 to gnd ........................................................-0.3v to +6v clken to gnd ....................................-0.3v to (v3p3 + 0.3v) d0Cd6 to gnd .....................................................-0.3v to +6v pgdin, dprstp to gnd .....................................-0.3v to +6v MAX8797 only: d0Cd4, stdby to gnd ........................................-0.3v to +6v max8796/max17401 32-pin, 5mm x 5mm tqfn continuous power dissipation (up to +70c) (derate above +70c/21.3mw/c) .....1702mw MAX8797 28-pin, 4mm x 4mm tqfn continuous power dissipation (up to +70c) (derate above +70c/20.8mw/c) .....1667mw operating temperature range .........................-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +165c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units pwm controller v cc , v dd 4.5 5.5 input voltage range v3p3 (max8796/max17401 only) 3.0 3.6 v dac codes from 0.8125v to 1.5000v -0.5 +0.5 % dac codes from 0.3750v to 0.8000v -7 +7 dc output-voltage accuracy measured at fb with respect to gnds; includes load-regulation error (note 3) dac codes from 0 to 0.3625v -20 +20 mv imvp-6 boot voltage v boot imvp-6 (max8796/max17401 only) 1.194 1.200 1.206 v line regulation error v cc = 4.5v to 5.5v, v in = 4.5v to 26v 0.1 % gnds input range -200 +200 mv gnds gain a gnds v ou t / v gn d s , - 20 0m v v gn d s + 20 0m v 0.97 1.00 1.03 v/v gnds input bias current i gnds -15 -10 +2 a time voltage v time v cc = 4.5v to 5.5v, i time = 28a (r time = 71.5k ) 1.985 2.000 2.015 v note 1: shdn can be forced to 12v for the purpose of debugging prototype breadboards using the no-fault test mode, which dis- ables fault protection.
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller _______________________________________________________________________________________ 3 confidential information?estricted to intel imvp-6 licensees parameter symbol conditions min typ max units r time = 71.5k (12.5mv/s nominal) -10 +10 r t im e = 35 .7 k ( 25m v / s n o m i nal ) to 17 8k (5mv/s nominal) -15 +15 soft-start and soft-shutdown; r time = 35.7k (3.125mv/s nominal) to 178k (0.625mv/s nominal) -20 +20 time slew-rate accuracy imvp-6 slow c4 exit (max8796/max17401 only) dprstp = dprslpvr = v cc ; r time = 35.7k (6.25mv/s nominal) to 178k (1.25mv/s nominal) -20 +20 % v in = 12v r ton = 96.75k 142 167 192 v fb = 1.2v r ton = 200k 300 333 366 on-time (note 4) t on r ton = 303.25k 425 500 575 ns minimum off-time t off ( min ) measured at dh (note 4) 300 375 ns ton shutdown input current shdn = gnd, v in = 26v, v cc = v dd = 0v or 5v, t a = +25c 0.01 1 a bias currents quiescent supply current (v cc )i cc measured at v cc , dprslpvr = 5v, fb forced above the regulation point 1.5 4 ma quiescent supply current (v dd )i dd measured at v dd , dprslpvr = 0v, fb forced above the regulation point, t a = +25c 0.02 1 a quiescent supply current (v3p3) (max8796/max17401 only) i 3p3 measured at v3p3, fb forced within the clken power-good window 24a shutdown supply current (v cc )m ea s u r ed at v c c , shdn = g n d , t a = + 25 c 0.01 1 a shutdown supply current (v dd )m ea s u r ed at v d d , shdn = g n d , t a = + 25 c 0.01 1 a shutdown supply current (v3p3) (max8796/max17401 only) m ea s u r ed at v 3p 3, shdn = g n d , t a = + 25 c 0.01 1 a fault protection skip mode after output reaches the regulation voltage or pwm mode; measured at fb with respect to typical vid target specified in table 3 (imvp-6) and table 4 (gmch) 250 300 350 mv imvp-6 (max8796 only) 1.75 1.80 1.85 s of t- st a r t, s o ft - sh u t d ow n, sk i p m od e, a n d out p ut ha v e no t r ea che d th e r eg ul at i on v o l ta g e; m ea s u r ed at f b gmch (max8796 with v3p3 = gnd and MAX8797) 1.50 1.55 1.60 output overvoltage-protection threshold (max8796/MAX8797 only) v ovp minimum ovp threshold; measured at fb 0.8 v electrical characteristics (continued) (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25c.) (note 2)
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 4 _______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees parameter symbol conditions min typ max units output overvoltage propagation delay (max8796/MAX8797 only) t ovp fb forced 25mv above trip threshold 10 s output undervoltage-protection threshold v uvp measured at fb with respect to typical vid target specified in table 3 (imvp-6) and table 4 (gmch) -450 -400 -350 mv output undervoltage propagation delay t uvp fb forced 25mv below trip threshold 10 s imvp-6 clken startup delay (boot time period, max8796/max17401 only) t boot imvp-6: max8796/max17401 v3p3 = 3.3v; measured from the time when fb reaches the boot target voltage (note 3); the time needed for fb to reach this target voltage is based on the slew rate set by r time 20 60 100 s imvp-6: max8796/max17401 v3p3 = 3.3v; measured at startup from the time when clken goes low 358ms pwrgd startup delay g m c h : m a x 8 79 7 o r m a x 879 6/m a x 174 01 v 3 p 3 = g n d ; mea s ur ed fr om th e t i me w hen fb r eac hes t he tar g e t v o l t ag e ( n ot e 3) ; th e ti me ne ed e d for fb t o r eac h thi s t a r g et v o l t ag e i s b a s e d o n the s l ew r a te s e t b y r ti me 20 60 100 s pwrgd standby wake-up delay gmch: MAX8797 or max8796/max17401 v3p3 = gnd; measured from the time when fb reaches the target voltage (note 3) based on the slew rate set by r time 20 s lower threshold, falling edge ( undervoltage) -350 -300 -250 pwrgd and clken (max8796/max17401 imvp-6 only) threshold me as ur e d a t fb w i t h r e s p ect to t y p i cal v i d ta r g et s p e c i f i e d i n tab l e 3 ( i m vp- 6 ) a n d t a bl e 4 (g m c h ); 50 mv hy s t er e s i s ( t y p ) upper threshold, rising edge ( overvoltage) +150 +200 +250 mv pwrgd and clken (max8796/max17401 imvp-6 only) transition blanking time t blank measured from the time when fb reaches the target voltage (note 3) based on the slew rate set by r time 20 s pwrgd and clken (max8796/ max17401 only) delay fb forced 25mv outside the pwrgd trip thresholds 10 s imvp-6 clken output low voltage (max8796/max17401 only) imvp-6: max8796/max17401, v3p3 = 3.3v; i sink = 3ma 0.4 v imvp-6 clken output high v ol t ag e ( m a x 8796/ma x 17401 o nl y ) imvp-6: max8796/max17401 v3p3 = 3.3v; i source = 3ma v 3p3 - 0.4 v pwrgd output low voltage i sink = 3ma 0.4 v pwrgd leakage current h i g h s t a t e, p w r g d f o r c ed to 5 v , t a = +2 5 c 1 a electrical characteristics (continued) (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25c.) (note 2)
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller _______________________________________________________________________________________ 5 confidential information?estricted to intel imvp-6 licensees parameter symbol conditions min typ max units v cc undervoltage lockout threshold v u v lo ( v c c ) rising edge, 65mv typical hysteresis, controller disabled below this level 4.05 4.27 4.48 v csn discharge resistance in uvlo and shutdown sh d n = gn d ; m eas ur ed w hen s o ft- s hutd ow n has b een com p l et e d ( d l p ul l ed l ow ) 8 thermal comparator and protection vrhot trip threshold measured at thrm with respect to v cc ; falling edge; typical hysteresis = 100mv 29.2 30 30.8 % vrhot delay t vrhot thrm forced 25mv below the vrhot trip threshold; falling edge 10 s vrhot output on-resistance r vrhot low state 2 8 vrhot leakage current i vrhot h i g h s t a t e, vrhot fo r ced to 5 v , t a = + 25 c 1 a thrm input leakage i thrm v thrm = 0 to 5v, t a = +25c -100 +100 na thermal-shutdown threshold t shdn typical hysteresis = 15c 160 c valley current limit and droop v time - v ilim = 100mv 7 1 0 13 current-limit threshold voltage (positive adjustable) v limit v csp - v csn v time - v ilim = 500mv 45 50 55 mv v csp - v csn imvp-6 (max8796/ max17401 only) 20 22.5 25 current-limit threshold voltage (positive default) ilim = v cc gmch (max8796/ m ax 17 40 1 v 3p 3 = g n d or MAX8797) 15 17.5 20 mv current-limit threshold voltage (negative) accuracy v li m i t ( n e g ) v csp - v csn , nominally -125% of v limit -4 +4 mv current-limit threshold voltage (zero crossing) v zero v pgnd - v lx , dprslpvr = v cc 1m v csp, csn common-mode input range 02 v csp, csn input current t a = +25c -0.2 +0.2 a ilim input current t a = +25c -100 +100 na droop amplifier (gmd) offset (v csp - v csn ) at i fb = 0 -0.75 +0.75 mv droop amplifier (gmd) transconductance i fb / (v csp - v csn ); fb = csn = 0.45v to 2.0v, and (v csp - v csn ) = -15.0mv to +15.0mv 592 600 608 s power monitor (pwr) v csn - v gnds = 1.200v v time - v ilim = 225mv, v csp - v csn = 15mv 1.95 2.00 2.05 power monitor output voltage for typical hfm conditions v pwr i pwr = 0a v time - v ilim = 500mv, v csp - v csn = 15mv 0.868 0.90 0.932 v power monitor gain referred to output voltage (v csn - v gnds ) a vpwr v time - v ilim = 225mv, v csp - v csn = 15mv 1.625 1.67 1.708 v/v electrical characteristics (continued) (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k < , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25c.) (note 2)
electrical characteristics (continued) (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units power monitor gain referred to current sense (v csp - v csn ) a ipwr v time - v ilim = 225mv , v csn - v gnds = 1.200v 122 133 144 v/v source: i pwr = 0a to 500a -3 power monitor load regulation v pwr measured at pwr with respect to unloaded voltage sink: i pwr = -100a 50 mv gate drivers high state ( pullup) 0.9 2.5 dh gate-driver on-resistance r on ( dh ) bst - lx forced to 5v low state ( pulldown) 0.7 2.0 high state ( pullup) 0.7 2.0 dl gate-driver on-resistance r on ( dl ) low state ( pulldown) 0.25 0.7 dh gate-driver source current i d h ( s ou r c e ) dh forced to 2.5v, bst - lx forced to 5v 2.2 a dh gate-driver sink current i dh ( sink ) dh forced to 2.5v, bst - lx forced to 5v 2.7 a dl gate-driver source current i d l ( s ou r c e ) dl forced to 2.5v 2.7 a dl gate-driver sink current i dl ( sink ) dl forced to 2.5v 8 a dh low to dl high 20 driver propagation delay (driver dead time) dl low to dh high 20 ns dl falling, c dl = 3nf 20 dl transition time dl rising, c dl = 3nf 20 ns dh falling, c dh = 3nf 20 dh transition time dh rising, c dh = 3nf 20 ns int e r nal bs t s w i tch o n- re s i s t ance r bst i bst = 10ma, v dd = 5v 10 20 logic and i/o logic input high voltage v ih max8796/max17401: shdn , dprslpvr, pgdin; MAX8797: shdn , dprslpvr; rising edge, typical hysteresis = 250mv 2.3 v logic input low voltage v il max8796/max17401: shdn , dprslpvr, pgdin; MAX8797: shdn , dprslpvr; falling edge, typical hysteresis = 250mv 1.0 v low-voltage logic input high voltage v ihlv max8796/max17401: dprstp , d0Cd6; MAX8797: stdby , d0Cd4; rising edge, typical hysteresis = 90mv 0.67 v low-voltage logic input low voltage v illv max8796/max17401: dprstp , d0Cd6; MAX8797: stdby , d0Cd4; falling edge, typical hysteresis = 90mv 0.33 v logic input current t a = +25c; max8796/max17401: shdn , dprslpvr, pgdin, dprstp , d0Cd6 = 0 or 5v; MAX8797: shdn , dprslpvr, stdby , d0Cd4 = 0 or 5v -1 +1 a max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 6 _______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller _______________________________________________________________________________________ 7 confidential informa tion?estricted to intel imvp-6 licensees electrical characteristics (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = -40? to +105? , unless otherwise specified.) (note 2) parameter symbol conditions min max units pwm controller v cc , v dd 4.5 5.5 input voltage range v 3p3 (max8796/max17401 only) 3.0 3.6 v dac codes from 0.8125v to 1.5000v -0.75 +0.75 % dac codes from 0.3750v to 0.8000v -10 +10 dc output-voltage accuracy measured at fb with respect to gnds; includes load-regulation error (note 3) dac codes from 0 to 0.3625v -25 +25 mv imvp-6 boot voltage v boot imvp-6 (max8796/max17401 only) 1.185 1.215 v gnds input range -200 +200 mv gnds gain a gnds v ou t / v gn d s , - 20 0m v v gn d s + 20 0m v 0.95 1.05 v/v time voltage v time v cc = 4.5v to 5.5v, i time = 28a (r time = 71.5k ) 1.98 2.02 v r time = 71.5k (12.5mv/s nominal) -10 +10 r time = 35.7k (25mv/s nominal) to 178k (5mv/s nominal) -15 +15 soft-start and soft-shutdown; r time = 35.7k (3.125mv/s nominal) to 178k (0.625mv/s nominal) -20 +20 time slew-rate accuracy imvp-6 slow c4 exit (max8796/max17401 only) dprstp = dprslpvr = v cc ; r time = 35.7k (6.25mv/s nominal) to 178k (1.25mv/s nominal) -20 +20 % v in = 12v r ton = 96.75k 142 192 v fb = 1.2v r ton = 200k 300 366 on-time (note 4) t on r ton = 303.25k 425 575 ns minimum off-time t off ( min ) measured at dh (note 4) 400 ns bias currents quiescent supply current (v cc )i cc measured at v cc , dprslpvr = 5v, fb forced above the regulation point 3m a quiescent supply current (v3p3) (max8796/max17401 only) i 3p3 measured at v3p3, fb forced within the clken power-good window 4 a
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 8 _______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees electrical characteristics (continued) (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = -40? to +105? , unless otherwise specified.) (note 2) parameter symbol conditions m i n m a x unit s f a u l t pr o t ec t i o n s k i p mod e aft er outp ut r e a c h e s t h e r e g u l a t i o n v o l t ag e or p w m m o d e ; me a s u r e d a t fb wi th r e s p ec t to t y p i ca l v i d tar g et s p e c i f i ed i n tab l e 3 ( i mv p - 6 ) and tab l e 4 ( g mc h ) 24 0 36 0 mv imv p - 6 ( m a x 8796 o n l y ) 1. 74 1.86 o u t p ut o v er v o l t ag e- p r otect i o n t h r es ho l d ( m a x 87 96 / m a x 8 7 9 7 o n l y ) v o vp s o ft- s t ar t, s o f t - s h u td ow n, s k i p m o de , a n d o u t pu t ha v e not r eache d the r e g u l a t i on v o l t a g e; m e a s ur ed a t f b g m c h ( m a x 87 96 w i t h v3 p3 = g n d or m a x 8 7 97) 1. 49 1. 61 v o u t p ut u n d e r v o l t a g e - p r o tect i o n t h r es ho l d v uv p me a s u r e d a t fb wi th r e s p ec t to t y p i ca l v i d tar g et s p e c i f i ed i n tab l e 3 ( i mv p - 6 ) and tab l e 4 ( g mc h ) - 460 - 340 mv imv p - 6 cl k e n st a r t u p d e l a y ( b oo t t i m e p e r i od , ma x 8 7 9 6 / ma x 1 740 1 o n l y ) t bo o t i m vp -6 : m a x8 7 9 6 / m a x1 7 4 0 1 v3 p3 = 3 . 3 v ; me a s u r e d f r o m t h e ti me w hen fb r e a ches th e b oot t a r g et v o l t ag e ( n ote 3) ; th e t i m e ne ed ed for fb t o r eac h th i s t a r g et v o l t ag e i s b a s e d o n th e s l ew r a t e s e t b y r ti me 20 10 0 s i m vp -6 : m a x8 7 9 6 / m a x1 7 4 0 1 v3 p3 = 3 . 3 v ; m e a s ur ed at s t ar tup f r om t h e t i m e w h e n cl k e n go e s l o w 3 8 ms p w r g d st a r t u p d e l a y g m c h : ma x 879 7 o r ma x 8 7 9 6 / ma x 1 740 1 v 3 p 3 = g n d ; me a s ur ed fr om t h e t i m e w h en fb r e a ches th e ta r g e t v o l t a g e ( n o t e 3) ; the t i m e n eed ed for f b t o r e a c h t h i s tar g et v o l t ag e i s b a s e d o n th e s l e w r a te s e t b y r tim e 20 10 0 s low er thr e s ho l d , f a llin g e d g e ( u nd er v o l t a g e ) - 360 - 240 p w r g d and cl k e n ( m a x 8 7 9 6 /ma x 17 401 im v p - 6 o nl y ) t h r es ho l d meas u r e d at f b wi th r e s p ect to t y p i ca l v i d t a r g e t s p e c if ie d in ta b l e 3 ( i m v p - 6 ) an d ta b l e 4 ( g m c h ) ; 50m v h y s t e r e s i s ( t y p ) u p pe r t h re s h o l d, r i s i ng ed g e (o v e r v o l t a ge ) +140 +260 mv imv p - 6 cl k e n o u tp ut low v o l t ag e ( m a x 8 79 6/ma x 17 401 o nl y ) i m vp -6 : m a x8 7 9 6 / m a x1 7 4 0 1 v3 p3 = 3 . 3 v ; i si n k = 3 m a 0. 4 v imv p - 6 cl k e n o u tp ut h i g h v o l t ag e ( m a x 8 79 6/ma x 17 401 o nl y ) i m vp -6 : m a x8 7 9 6 / m a x1 7 4 0 1 v3 p3 = 3 . 3 v ; i s o ur ce = 3ma v3 p3 - 0. 4 v p w r g d o u t p ut l o w v o l t ag e i si n k = 3 m a 0. 4 v v cc u n der v ol ta g e lock out ( u v l o ) thr e s ho l d v uv l o ( v cc) r i s i ng ed g e , 65 mv t y p i c a l h y s t er e s i s , c o n t r o l le r d i sa b l e d b e lo w t h i s le ve l 4. 0 4. 5 v
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller _______________________________________________________________________________________ 9 confidential informa tion?estricted to intel imvp-6 licensees electrical characteristics (continued) (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = -40? to +105? , unless otherwise specified.) (note 2) parameter symbol conditions min typ max units thermal comparator and protection vrhot trip threshold measured at thrm with respect to v cc ; falling edge; typical hysteresis = 100mv 29 31 % vrhot output on-resistance r vrhot low state 8 valley current limit and droop v time - v ilim = 100mv 7 1 3 current-limit threshold voltage (positive adjustable) v limit v csp - v csn v time - v ilim = 500mv 45 55 mv v csp - v csn imvp-6 (max8796/ max17401 only) 20 25 current-limit threshold voltage (positive default) ilim = v cc gmch (max8796/ max17401 v3p3 = gnd or MAX8797) 15 20 mv current-limit threshold voltage (negative) accuracy v li m i t ( n e g ) v csp - v csn , nominally -125% of v limit -5 +5 mv csp, csn common-mode input range 02 v droop amplifier (gmd) offset ( v csp - v csn ) at i fb = 0 -1.0 +1.0 m v droop amplifier (gmd) transconductance i fb / (v csp - v csn ); fb = csn = 0.45v to 2.0v, and (v csp - v csn ) = -15.0mv to +15.0mv 588 612 s power monitor (pwr) v csn - v gnds = 1.200v v time - v ilim = 225mv, v csp - v csn = 15mv 1.92 2.08 power monitor output voltage for typical hfm conditions v pwr i pwr = 0a v time - v ilim = 500mv, v csp - v csn = 15mv 0.85 0.95 v power monitor gain referred to output voltage (v csn - v gnds ) a vpwr v time - v ilim = 225mv, v csp - v csn = 15mv 1.583 1.750 v/v power monitor gain referred to current sense (v csp - v csn ) a ipwr v time - v ilim = 225mv, v csn - v gnds = 1.200v 122 144 v/v power monitor load regulation v pwr measured at pwr with respect to unloaded voltage source: i pwr = 0a to 500a -3 mv
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 10 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees note 2: limits are 100% production tested at t a = +25c. maximum and minimum limits over temperature are guaranteed by design and characterization. note 3: the equation for the target voltage v target is: v target = the slew-rate-controlled version of v dac , where v dac = 0 for shutdown, v dac = v boot (imvp-6) or v vid (gmch) during startup, and v dac = v vid otherwise (the v vid voltages for all possible vid codes are given in tables 3 and 4). in pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. note 4: on-time and minimum off-time specifications are measured from 50% to 50% at the dh pin, with lx forced to 0v, bst forced to 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times can be different due to mosfet switching speeds. electrical characteristics (continued) (circuit of figure 1 (max8796/max17401), circuit of figure 2 (MAX8797), v in = 12v, v dd = v cc = 5v, v3p3 = 3.3v, shdn = stdby = dprstp = ilim = pgdin = v cc , dprslpvr = gnds = pgnd = gnd, r fb = 4.25k , v cc_sense = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100 for imvp-6, d0Cd4 = 01000 for gmch). t a = -40? to +105? , unless otherwise specified.) (note 2) parameter symbol conditions min typ max units gate drivers high state (pullup) 2.5 dh gate-driver on-resistance r on ( dh ) bst - lx forced to 5v low state ( pulldown) 2.0 high state (pullup) 2.0 dl gate-driver on-resistance r on ( dl ) low state (pulldown) 0.7 internal bst switch on-resistance r bst i bst = 10ma, v dd = 5v 20 logic and i/o logic input high voltage v ih max8796/max17401: shdn , dprslpvr, pgdin; MAX8797: shdn , dprslpvr; rising edge, typical hysteresis = 250mv 2.3 v logic input low voltage v il max8796/max17401: shdn , dprslpvr, pgdin; MAX8797: shdn , dprslpvr; falling edge, typical hysteresis = 250mv 1.0 v low-voltage logic input high voltage v ihlv max8796/max17401: dprstp , d0Cd6; MAX8797: stdby , d0Cd4; rising edge, typical hysteresis = 90mv 0.67 v low-voltage logic input low voltage v illv max8796/max17401: dprstp , d0Cd6; MAX8797: stdby , d0Cd4; falling edge, typical hysteresis = 90mv 0.33 v
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 11 max8796/max17401 0.9v output efficiency vs. load current max8796 toc01 load current (a) efficiency (%) 10 1 0.1 60 70 80 90 100 50 0.01 100 12v 20v skip mode pwm mode 7v max8796/max17401 0.9v output voltage vs. load current max8796 toc02 load current (a) output voltage (v) 20 15 10 5 0.86 0.88 0.90 0.92 0.84 02 5 skip mode pwm mode max8796/max17401 0.65v output efficiency vs. load current max8796 toc03 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 12v 20v 7v skip mode pwm mode max8796/max17401 0.65v output voltage vs. load current max8796 toc04 load current (a) output voltage (v) 8 6 4 2 0.64 0.63 0.65 0.66 0.67 0.62 01 0 skip mode pwm mode MAX8797 output efficiency vs. load current max8796 toc05 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 12v 20v 7v skip mode pwm mode MAX8797 output voltage vs. load current max8796 toc06 load current (a) output voltage (v) 8 6 4 2 1.02 1.06 1.04 1.00 1.08 1.10 1.12 0.98 01 0 skip mode pwm mode max8796/max17401 switching frequency vs. load current max8796 toc07 load current (a) switching frequency (khz) 10 1 0.1 100 200 300 400 500 0 150 250 350 450 50 0.01 100 v out = 0.9v v out = 0.65v skip mode pwm mode MAX8797 switching frequency vs. load current max8796 toc08 input voltage (v) switching frequency (khz) 1 0.1 50 150 100 200 250 300 0 0.01 10 skip mode pwm mode max8796/max17401 v out = 0.9v no-load supply current vs. input voltage max8796 toc09 input voltage (v) supply current (ma) 18 12 1 10 100 0.1 62 4 15 92 1 i cc + i dd (pwm) i cc + i dd (skip) i in (pwm) i in (skip) skip mode pwm mode t ypical operating characteristics (t a = +25c, unless otherwise noted. max8796/max17401: circuit of figure 1 core 2 duo ulv. MAX8797: circuit of figure 2 crestline.) confidential informa tion?estricted to intel imvp-6 licensees
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 12 ______________________________________________________________________________________ t ypical operating characteristics (continued) (t a = +25c, unless otherwise noted. max8796/max17401: circuit of figure 1 core 2 duo ulv. MAX8797: circuit of figure 2 crestline.) max8796/max17401 v out = 0.65v no-load supply current vs. input voltage max8796 toc10 input voltage (v) supply current (ma) 18 12 1 10 100 0.1 62 4 15 92 1 i cc + i dd (pwm) i cc + i dd (skip) i in (pwm) i in (skip) skip mode pwm mode MAX8797 no-load supply current vs. input voltage max8796 toc11 input voltage (v) i bias (ma) 18 12 1 10 100 0.1 62 4 15 92 1 i cc + i dd (pwm) i cc + i dd (skip) i in (pwm) skip mode pwm mode i in (skip) max8796/max17401 power monitor vs. load current max8796 toc12 load current (a) power monitor (v) 20 15 10 5 1.0 2.0 3.0 0 0.5 1.5 2.5 02 5 v out = 0.9v max8796/max17401 power monitor vs. output voltage max8796 toc13 output voltage (v) power monitor (v) 1.4 1.0 0.6 0.4 1.2 0.8 0.2 2.0 0 0.5 1.0 1.5 01 .6 10a load 0.8125v output voltage distribution max8796 toc14 output voltage (v) sample percentage (%) 70 0 40 50 60 10 20 30 0.8075 0.8085 0.8095 0.8105 0.8115 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175 sample size = 100 +85 c +25 c g m (fb) transconductance distribution max8796 toc15 transconductance ( s) sample percentage (%) 0 40 50 60 10 20 30 590 592 594 596 598 600 602 604 606 608 610 sample size = 100 +85 c +25 c confidential informa tion?estricted to intel imvp-6 licensees
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 13 max8796/max17401 imvp-6 soft-start waveform (up to clken) max8796 toc16 200 s/div a. shdn, 5v/div b. clken, 3.3v/div c. v out , 500mv/div d. inductor current, 5a/div 0 3.3v 0 5v 0 0.9v 0 b a d c max8796/max17401 imvp-6 soft-start waveform (up to pwrgd) max8796 toc17 1ms/div a. pgdin, 5v/div b. pwrgd, 5v/div c. clken, 3.3v/div d. v out , 500mv/div e. inductor current, 5a/div 0 5v 3.3v 0 5v 0 0.9v 0 0 b a d e c max8796/max17401 imvp-6 shutdown waveform max8796 toc18 100 s/div a. shdn, 5v/div b. clken, 3.3v/div c. pwrgd, 5v/div e. dl, 5v/div d. v out , 1v/div f. inductor current, 5a/div 0 3.3v 5v 0 5v 0 0.9v 5v 0 0 b a d e f c MAX8797 gmch soft-start waveform max8796 toc19 100 s/div a. shdn, 5v/div b. pwrgd, 5v/div c. v out , 500mv/div d. inductor current, 5a/div 0 5v 1.0815v 0 5v 0 0 b a d c MAX8797 gmch shutdown waveform max8796 toc20 100 s/div a. shdn, 5v/div b. pwrgd, 5v/div c. dl, 5v/div d. v out , 500mv/div e. inductor current, 5a/div 0 5v 5v 1.0815v 0 5v 0 0 0 b a d e c max8796/max17401 load-transient response (imvp-6 hfm mode) max8796 toc21 20 s/div a. i out = 5.5 to 23a, 10a/div b. v out , 50mv/div c. inductor current, 10a/div 5.5a 5.5a 0.9v 23a 23a 0.863v b a c t ypical operating characteristics (continued) (t a = +25c, unless otherwise noted. max8796/max17401: circuit of figure 1 core 2 duo ulv. MAX8797: circuit of figure 2 crestline.) confidential informa tion?estricted to intel imvp-6 licensees
entering deeper sleep exiting to lfm max8796 toc24 40 s/div a. dprstp, 5v/div b. dprslpvr, 5v/div i out = 1a c. v out , 200mv/div d. inductor current, 10a/div 0 0 5v 0 5v 0.9v b a c d max8796/max17401 load-transient response (imvp-6 lfm mode) max8796 toc22 20 s/div a. i out = 3.5a to 9.5a, 5a/div b. v out , 20mv/div c. inductor current, 10a/div 3.5a 3.5a 9.5a 9.5a 0.8375v 0.825v b a c MAX8797 load-transient response max8796 toc23 20 s/div a. i out = 1.5a to 8a, 5a/div b. v out , 50mv/div c. inductor current, 5a/div 1.5a 1.5a 8a 8a 1.0815v 1.03v b a c max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 14 ______________________________________________________________________________________ t ypical operating characteristics (continued) (t a = +25c, unless otherwise noted. max8796/max17401: circuit of figure 1 core 2 duo ulv. MAX8797: circuit of figure 2 crestline.) entering deeper sleep exiting to nearest vid max8796 toc25 20 s/div a. dprstp, 5v/div b. dprslpvr, 5v/div i out = 0.3a c. v out , 20mv/div d. inductor current, 10a/div 0 0 5v 0 5v 0.9v b a c d entering deeper sleep exiting to lfm max8796 toc26 40 s/div a. dprstp, 5v/div b. dprslpvr, 5v/div i out = 2a c. v out , 200mv/div d. inductor current, 10a/div 0 0 5v 0 5v 0.9v b a c d d0 12.5mv dynamic vid code change max8796 toc27 10 s/div a. d0, 5v/div b. v out , 20mv/div c. inductor current, 2a/div 0 0 5v 0.9v 0.8875v b a c confidential information?estricted to intel imvp-6 licensees
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 15 d2 50mv dynamic vid code change max8796 toc28 10 s/div a. d2, 5v/div b. v out , 50mv/div c. inductor current, 2a/div 0 0 5v 0.9v 0.85v b a c output overload waveform max8796 toc29 100 s/div a. load current, 25a/div b. pgood, 5v/div c. v out , 1v/div d. dl, 5v/div e. inductor current, 25a/div 0 0 0 25a 5v 0 5v 0 25a 0.9v b a c d e output overvoltage waveform max8796 toc30 40 s/div a. v out , 500mv/div b. dl, 5v/div c. pwrgd, 5v/div 0 0 0.9v 5v 0 5v b a c bias supply removal (uvlo response) max8796 toc31 200 s/div a. 5v bias supply, 5v/div b. v out , 500mv/div c. dl, 5v/div d. pgood, 5v/div e. inductor current, 10a/div 0 0 5v 0.9v 5v 0 0 5v 10a b a c d e power monitor - vid transition response (i out = 10a) max8796 toc32 40 s/div a. d4, 5v/div b. v out , 200mv/div c. p out with rc filter, 1v/div d. p out , 1v/div e. inductor current, 10a/div 0 0 5v 0.9v 0.7v 0 0 1.05v 1.05v 10a b a c d e t ypical operating characteristics (continued) (t a = +25c, unless otherwise noted. max8796/max17401: circuit of figure 1 core 2 duo ulv. MAX8797: circuit of figure 2 crestline.) confidential informa tion?estricted to intel imvp-6 licensees
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 16 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees pin description pin max8796/ max17401 MAX8797 name function 1 1 pwr power monitor output. the voltage on pwr is directly proportional to the amount of power being delivered to support the load: where k pwr = 25 is the power monitor scale factor. the max8796/MAX8797/max17401 pull pwr to ground when the controller is disabled. 2 2 gnds re m ot e g r ou nd - s en s e in p ut. c on nec t d i r ec tl y to t h e c p u or gm c h v s s se n s e p i n ( g r ou nd s e ns e) or d i r ec tl y to t he g r ou nd co nne ct i on of t h e l oa d . g n d s i nt er na l l y co nn ec t s to a tr an s c ond u ct a nc e am p l i fi er th at ad j u s ts t h e fe ed b a c k vo l ta g e, co m p ens at i ng fo r vo l ta g e d r op s b et w ee n t he r eg ul at o r s g r ou nd an d the p r o ces s o r s g r o und . 3 3 fb rem ot e- s en s e fe ed b ack i n p ut a n d v ol tag e- p os i ti on i ng tr an s c ond u ct a nc e a m p l i fi er ou t p ut . c on ne ct a r es i st o r r f b b et w ee n f b and t h e ou tp ut r em o t e s e ns e ( v c c _ s e n s e ) to s e t th e s t e a d y- s t at e d r oo p b as ed on th e v o l ta g e- p os i ti on i ng g ai n r eq ui r em en t : r f b = r d roop / ( r s e n s e x g m d ) w he r e r d ro o p i s the d es i r ed vo l ta g e- p os i ti oni ng sl op e, g m d = 600s ty p and r s e n s e i s t h e cur r ent- sense r esi stance w i th r esp ect to the c s p - to- c s n cur r ent- sense i np uts. s ee the c ur r ent s en s e se c t i on for d et a i l s on d es i g ni ng w i th s ens e r es i st o r s o r i nd uc tor d c r s ens i ng . s ho r ti ng fb d i r ectl y to the outp u t effe cti ve l y d i sa b l es v o l tag e p os i ti oni ng , b ut i m p act s the s t ab i l i ty r eq ui r em e n ts . d es i g ns that d i sa b l e v ol ta g e p os i ti on i ng r eq ui r e a hi g he r m i ni m um o u tp ut cap aci tan ce e s r to m ai ntai n s t a b i l i ty ( s ee th e ou t p ut c ap aci to r s el ec t i on se c t i on) . fb e n ter s a hi g h- i m p ed ance state i n shutd ow n. 4 4 csn negative inductor current-sense input. connect csn to the negative terminal of the inductor current-sensing resistor or directly to the negative terminal of the inductor if the lossless dcr sensing method is used (see figure 4). the max8796/MAX8797/max17401 also use csn as the voltage input to the power monitor. under v cc uvlo conditions and after soft-shutdown is completed, csn is internally pulled to gnd through a 10 fet to discharge the output. 5 5 csp positive inductor current-sense input. connect csp to the positive terminal of the inductor current-sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless dcr sensing method is used (see figure 4). deeper stop input and slew-rate control signal (max8796/max17401 only). this 1v logic input signal from the system is usually the logical complement of the dprslpvr signal. however, there is a special condition during c4 exit when both dprstp and dprslpvr could temporarily be simultaneously high. if this happens, the max8796/max17401 reduce the slew rate to 1/4 the nominal (r time -based) slew rate for the duration of this condition. the slew rate returns to nominal when this condition is exited. note that only dprslpvr (and not dprstp ) determines the mode of operation (pwm vs. skip). dprslpvr dprstp functionality 0 x nominal slew rate, 1-phase forced-pwm mode (dprslpvr low dprstp is ignored) 1 0 nominal slew rate, 1-phase skip mode 1 1 slew rate reduced to 1/4 of nominal, 1-phase skip mode 6 dprstp the dprstp state is ignored during soft-start and shutdown. the max8796/MAX8797/ max17401 always use 1/8 of nominal slew rate during startup to minimize the surge current. during shutdown, the controller always uses 1/8 of the nominal slew rate to provide a soft- shutdown to avoid excessive output ringing below ground. v kv v v v vv pwr pwr csn gnds csp csn time ilim = () ( ) ()
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 17 confidential information?estricted to intel imvp-6 licensees pin description (continued) pin max8796/ max17401 MAX8797 name function deeper sleep status signalpulse-skipping and slew-rate control input. the dprslpvr signal indicates the imvp-6 power usage and sets the operating mode of the max8796/ MAX8797/max17401. when the system forces dprslpvr high, the max8796/MAX8797/ max17401 immediately enter automatic pulse-skipping mode. the controller returns to continuous forced-pwm mode when dprslpvr is pulled low and the output is in regulation. dprslpvr determines the operating mode and output-voltage-transition slew rate as shown in the truth table below: dprslpvr dprstp functionality 0 x nominal slew rate, 1-phase forced pwm mode (dprslpvr low dprstp is ignored) 1 0 nominal slew rate, 1-phase skip mode 1 1 slew rate reduced to 1/4 of nominal, 1-phase skip mode 7 6 d p rs lp v r the dprslpvr state is ignored during soft-start and shutdown. the max8796/MAX8797/ max17401 always use pulse-skipping mode during startup to ensure a monotonic power- up. during shutdown, the controller always uses forced-pwm mode so the output can be actively discharged. 8 7 thrm comparator input for thermal protection. thrm connects to the positive input of an internal comparator. the comparators negative input connects to an internal resistive voltage- divider that accurately sets the thrm threshold to 30% of the v cc voltage. connect the output of a resistor and thermistor divider (between v cc and gnd) to thrm with the values selected so the voltage at thrm falls below 30% of v cc (1.5v when v cc = 5v) at the desired hi g h tem p erature. 9 8 ton switching frequency setting input. an external resistor (r ton ) between the input power source and ton sets the switching frequency (f sw = 1/t sw ) according to the following equation used to determine the nominal switching period: t sw = 16.3pf x (r ton + 6.5k ) ton enters high impedance in shutdown to reduce the input quiescent current. if the ton current is less than 10a, the max8796/MAX8797/max17401 disable the controller, set the ton open fault latch, and pull dl and dh low. 10 9 pwrgd open-drain power-good output. the max8796/MAX8797/max17401 force pwrgd low when shdn , pgdin, or stdby are pulled low. after the controller is properly powered up, pwrgd becomes a high-impedance output as long as the feedback voltage is in regulation and the startup blanking time has expired: im v p - 6 ( m ax 8 796 /m ax 1 740 1 v 3p 3 = 3. 3v ) : p wr g d b e com es ac ti ve 5 m s a f t e r t he m ax 87 96/ max17401 pull clken low. the max8796/max17401 pull pwrgd low when shut down ( shdn = gnd) or the power-good input (pgdin = gnd) is pulled low, and during the startup and shutdown transitions. gmch (MAX8797 or max8796/max17401 v3p3 = gnd): pwrgd becomes active 60s after the soft-start sequence has been completed. the max8796/MAX8797/max17401 pull pwrgd low when shutdown ( shdn = gnd) or standby ( stdby = gnd) are pulled low, and during the startup and shutdown transitions. th e p wr g d up p er th r es ho l d i s b l an k e d d ur i ng an y d ow nw ar d ou tp ut - vo l ta g e t r an s i ti on t h at oc cu r s w he n t he m ax 87 96 /m ax 87 97 / m ax 174 01 a r e i n s k i p m od e ( d p rs lp v r p ul l ed hi g h) . pwrgd remains blanked until the transition-related pwrgd blanking period expires and the controller detects the output is in regulation (error amplifier edge occurs). note: the pullup resistance on pwrgd causes additional shutdown current.
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 18 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees pin description (continued) pin max8796/ max17401 MAX8797 name function 11 10 shdn shutdown control input. connect to v cc for normal operation. connect to ground to put the controller into the low-power 1a (max) shutdown state. during startup, the controller ramps up the output voltage at 1/8 the slew rate set by the time resistor to the target voltage defined by the application circuit: im v p - 6 ( m ax 8796 /m ax 17 401 v 3p 3 = 3. 3 v ) st a r tup tar g et = th e 1.2v b oot v o l tag e g m c h ( m ax 8797 or m ax 8796/m ax 1740 1 v 3p 3 = gn d ) st a r tup ta r g et = vo l ta g e s e t b y t h e v id i np uts during the shutdown transition, the max8796/MAX8797/max17401 softly ramp down the output voltage at 1/8 the slew rate set by the time resistor. forcing shdn to 11v ~ 13v disables overvoltage protection (ovp), undervoltage protection (uvp), and thermal shutdown, and clears the fault latches. 12 clken imvp-6 clock enable output (max8796/max17401 only). clken uses cmos push-pull logic so no external pullup resistor is necessary. this active-low logic output indicates when the feedback voltage is in regulation. the max8796/max17401 force clken low during dynamic vid transitions and for an additional 20s after the vid transition is completed. clken is the inverse of pwrgd, except for the 5ms pwrgd startup delay period after clken is pulled low. see the startup timing diagram (figure 11). the clken upper threshold is blanked during any downward output voltage transition that happens when the max8796/max17401 are in skip mode, and stays blanked until the transition- related pwrgd blanking period is complete and the output reaches regulation. 13 v3p3 3.3v clken input supply (max8796/max17401 only). v3p3 input supplies the clken cmos push-pull logic output. connect to the systems standard 3.3v supply voltage before shdn is pulled high for proper imvp-6 operation. connect v3p3 = gnd to select the intel gmch vid code and feature set. 14C20 11C15 d0Cd6 (gmch: d0Cd4) low-voltage (1.0v logic) vid dac code inputs. the d0Cd6 (imvp-6) or d0Cd4 (gmch) inputs do not have internal pullups. these 1.0v logic inputs are designed to interface directly with the cpu. the output voltage is set by the vid code indicated by the logic level voltages on d0Cd6 (imvp-6, see table 3) or d0Cd4 (gmch, see table 4). the max8796/max17401 can be configured to support either imvp-6 (v3p3 = 3.3v) or gmch (v3p3 = gnd) applications. when configured for the gmch code set, pin 14 to pin 18 of the max8796/max17401 serve as the d0 to d4 vid inputs (respectively) and pin 19 provides the standby function. 16 stdby gmch standby logic input (gmch). stdby is low-voltage logic input (1v logic) similar to those used on the vid inputs. when stdby is pulled low, the gmch controller enters standby mode and actively slews down the output to 0v at 1/8 the slew rate set by the time resistance. once the output is discharged, the controller enters a high-impedance output state (dh and dl pulled low). when stdby is forced high, the controller exits standby mode (while in skip mode) and slews the output voltage to the target voltage set by the vid code at 1/4 the slew rate set by the time resistance. shdn always overrides the stdby signal. when the max8796/max17401 are configured for the gmch code set (v3p3 = gnd), pin 14 to pin 18 of the max8796/max17401 serve as the d0 to d4 gmch vid inputs (respectively) and pin 19 provides the standby function. 21 17 pgnd power ground. ground connection for the dl driver.
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 19 confidential information?estricted to intel imvp-6 licensees pin description (continued) pin max8796/ max17401 MAX8797 name function 22 18 dl low-side gate-driver output. dl swings from v dd to pgnd. dl is forced low in shutdown. dl is forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. dl is forced low in skip mode after detecting an inductor current zero crossing. 23 19 v dd d r i ve r - s up p l y v ol ta g e i np ut . v d d su p p l i es p ow er to t he l ow - si d e g at e d r i ve r ( d l) an d to th e i nt er na l bs t s w i tc h us e d to r ef r es h the b s t cap aci to r . c on ne ct v d d t o the 4. 5v to 5. 5v sy st e m su p p l y vo l ta g e. b y p a ss v d d to p gn d w i t h a 1 f or g r ea te r cer am i c cap ac i to r . 24 20 bst boost flying capacitor connection. bst provides the upper supply rail for the dh high- side gate driver. an internal switch between v dd and bst charges the flying capacitor while the low-side mosfet is on (dl pulled high and lx pulled to ground). 25 21 lx in d uc to r c o nne ct i on . l x se r v e s as t he l ow er su p p l y r ai l fo r th e d h hi g h- si d e g ate d r i ve r . the m ax 8796/m ax 8797/m ax 17401 al so use lx as the i np ut to the zer o- cr ossi ng com p ar ator . 26 22 dh high-side gate-driver output. dh swings from lx to bst. the controller pulls dh low in shutdown. 23 gnd analog ground. connect to the exposed backside pad and low-current analog ground terminations. 27 pgdin im v p - 6 p ow er - go o d log i c i np ut ( m ax 8 796 /m ax 174 01 o nl y) . p gd in i nd i c a te s the p ow er s t at us of ot her sy st e m r ai l s us ed to p ow er t he chi p s e t and c p u v c c p su p p l i es . f o r t h e im v p - 6 ( v 3p 3 = 3. 3v ) , th e m ax 8 796 /m ax 174 01 p ow er up an d r em ai n at t h e b oo t v o l tag e ( v b oo t ) as l on g as p g d in r em ai ns l ow . w h en p g d in i s f o r ce d hi g h, t h e m ax 87 96 /m ax 17 401 t r an s i ti on th e ou tp u t to th e v o l ta g e s e t b y t h e v id co d e , and c lk e n i s a l l ow ed to g o l ow . if pgdin is pulled low at any time, the max8796/max17401 immediately force c lk e n high and pwrgd low and sets the output to the boot voltage. the output remains at the boot voltage until the system either disables the controller or until pgdin goes high again. pgdin is only active for imvp-6 configurations (v3p3 = 3.3v). for gmch applications (v3p3 = gnd), the pgdin input is blanked high. 28 24 vrhot th er m al c om p ar at o r s op en- d r ai n o ut p ut. th e com p ar at or p ul l s vr h o t l ow w h en th e v o l ta g e at th rm d r op s b el ow 30 % o f v c c ( 1. 5 v w i th 5v x v c c ) . vr h ot i s h i g h i m p ed a nce i n s hutd ow n. 29 25 time slew-rate adjustment. time regulates to 2.0v and the load current determines the slew rate of the internal error-amplifier target. the sum of the resistance between time and gnd (r time ) determines the nominal slew rate: slew rate = (12.5mv/s) x (71.5k / r time ) th e g ua r an te ed r ti m e r an g e i s b et w e en 35 .7k an d 17 8k . th i s nom i na l sl ew r at e a p p l i es to v id tr an s i ti ons an d to the t r an s i ti on fr om b oot m od e to v id . if th e v id d ac i np uts a r e cl oc k e d , th e s l ew r at e f or al l ot h e r v id tr an s i ti on s i s se t b y t he r a t e at w hi ch th ey ar e c l oc k e d , up to a m ax i m um sl ew r a t e eq ual to t he nom i na l sl ew r at e d ef i ne d ab ov e . the startup and shutdown slew rates are always 1/8 of nominal slew rate to minimize surge currents. for imvp-6 (max8796/max17401 v3p3 = 3.3v), if dprslpvr and dprstp are both high, then the slew rate is reduced to 1/4 of nominal. for gmch (MAX8797 or max8796/max17401 v3p3 = gnd), the slew rate for wakeup from standby is 1/4 of nominal, but the slew rate when entering standby is 1/8 of nominal.
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 20 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees pin description (continued) pin max8796/ max17401 MAX8797 name function 30 26 ilim valley current-limit adjustment input. the valley current-limit threshold voltage at csp to csn equals precisely 1/10 of the differential time to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). the negative current-limit threshold is nominally - 125% of the corresponding valley current-limit threshold. connect ilim directly to v cc to set the default current-limit threshold setting of 22.5mv nominal for imvp-6 (max8796/max17401 v3p3 = 3.3v) and 17.5mv nominal for gmch (MAX8797 and max8796/max17401 v3p3 = gnd). 31 27 v cc an a l og s up p l y v ol tag e. c onn ect to a 4.5 v to 5 . 5v so u r ce. b y p as s to g n d w i th 1f m i ni m um . 32 28 ccv integrator capacitor connection. connect a capacitor (c ccv ) from ccv to gnd to set the integration time constant. choose the capacitor value according to: 16 x [c ccv / g m(ccv) ] x f sw >> 1 where g m(ccv) = 320s (max) is the integrators transconductance and f sw is the switching frequency set by the r ton resistance. the integrator is internally disabled during any downward output voltage transition that occurs in pulse-skipping mode, and remains disabled until the transition blanking period expires and the output reaches regulation (error amplifier transition detected). pad (gnd) analog ground and exposed pad (back side). internally connected to gnd. connect to the ground plane through a thermally enhanced via. note: for the max8796/max17401, this is the only gnd pin .
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 21 confidential information?estricted to intel imvp-6 licensees pwrgd v cc v dd shdn on off time gnds r pwrgd 10k r thrm 7.87k ntc2 100k b = 4700 3.3v (vron) r1 12.1k l1 n lo n hi c out lx dh dl bst pgnd csp csn pwr r3 10k ton fb v cc c pwr 0.1 f 10 1 29 8 9 3 2 4 5 31 23 22 21 25 26 24 11 d1 r5 1.00k r7 10k r6 1.50k ntc1 10k b = 4500 thrm vcc_sense vss_sense load-line adjustment : r fb = r droop /(r sense x 600 s) dcr thermal compensa tion pwr pwr pwr agnd ilim 30 r2 59.0k v alley current limit set by time to ilim v limit = 0.2v x r1/(r2 + r1) slew ra te set by time bias current dv/dt = 12.5mv/ s x 71.5k / (r2 + r1) core output gnd (ep) agnd agnd dprstp 6 dprslpvr 7 clken 12 v3p3 13 ccv 32 agnd agnd agnd pgdin 27 d0 d1 d2 d3 d4 vid inputs 14 15 16 17 18 d5 19 d6 20 vrhot 28 remote-sense inputs remote-sense filters switching frequency (f sw = 1/t sw ): t sw = 16.3pf x (r ton + 6.5k ) r16 10 r15 10 ca tch resistors required when cpu not popula ted agnd r gnd 0 c ccv 100pf c9 1000pf r fb 2.4k 1% r13 10 pwr 33 r4 open c4 sleep control system i/o power-good agnd c in pwr max8796 max17401 pwr r vrhot 10k agnd c csp open c bst 0.1 f r bst 0 r ton 120k agnd c vcc 1.0 f c vdd 1.0 f r vcc 10 c sense 0.1 f agnd c csn open c10 1000pf r14 10 input 7v to 24v 5v bias input figure 1. max8796/max17401 imvp-6 application circuit
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 22 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees design parameters santa rosa core 2 duo lv santa rosa core 2 duo ulv centrino ulv core solo silverthorne umpc/lpia core input voltage range 7v to 20v 7v to 20v 7v to 20v 4.5v to 8.0v maximum load current 23a (30a ocp) 17a (21a ocp) 8a (10a ocp) 4a (5a ocp) transient load current 19a (10a/s) 14a (10a/s) 5.5a (5a/s) 3.6a (2.5a/s) load line 2.1mv/a 2.1mv/a 5.1mv/a 5.7mv/a components ton resistance (r ton ) 200k (f sw = 300khz) 150k (f sw = 400khz) 120k (f sw = 500khz) 120k (f sw = 500khz) inductance (l) nec/tokin mpc1055lr36 0.36h, 32a, 0.8m nec-tokin mpc0730lr20 1h, 25a, 1.0m v i sh a y - d al e ih lp - 2 525 c z - 07 0.47h, 17a, 3.86m nec-tokin mplc0525l1r0 1h, 7a, 14m high-side mosfet (n h ) siliconix si4386dy 7.8m /9.5m (typ/max) fairchild fds6298 9.4m /12m (typ/max) siliconix si4386dy 7.8m /9.5m (typ/max) low-side mosfet (n l ) 2x siliconix si4642dy 3.9m /4.7m (typ/max) fairchild fds8670 4.2m /5.0m (typ/max) siliconix si4642dy 3.9m /4.7m (typ/max) fairchild fds6982s nh: 28m /35m (typ/max) nl: 17m /22m (typ/max) output cap (c out ) panasonic 4x 330f, 6m , 2.5v eefsx0d0d331xr 32x 10f, 6v ceramic (0805) 6x 100f, 4v ceramic (1210) 32x 10f, 6v ceramic (0805) sanyo 2x 220f, 7m , 2.0v 2tpf220m7 12x 10f, 6v ceramic (0805) 2x 47f, 6v ceramic (1210) 2x 10f, 6v ceramic (0805) input cap (c in ) 4x 10f, 25v ceramic (1210) 3x 10f, 25v ceramic (1210) 2x 10f, 25v ceramic (1210) 1x 10f, 16v ceramic (1206) time/ilim resistance (r1) 6.19k 4.42k 12.1k 17.8k ilim/gnd resistance (r2) 64.9k 66.5k 59.0k 53.6k fb resistance (r fb ) 4.99k 4.42k 2.49k 1.05k lx/csp resistance (r5) 1.00k 2.20k 1.00k 1.13k csp/csn series resistance (r6) 1.50k 2.37k 1.50k 2.26k parallel ntc resistance (r7) 10.0k 15k 10.0k open dcr sense ntc (ntc1) 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f short dcr sense capacitance (c sense ) 0.47f, 6v ceramic (0805) 0.1f, 6v ceramic (0603) 0.1f, 6v ceramic (0603) 0.1f, 6v ceramic (0603) table 1. imvp-6 component selection
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 23 confidential information?estricted to intel imvp-6 licensees pwrgd v cc v dd shdn on off time gnds r pwrgd 10k r thrm 7.87k ntc2 100k b = 4700 3.3v (vron) r1 8.06k l1 n lo n hi c out lx dh dl bst pgnd csp csn pwr r3 10k ton fb v cc c8 0.1 f 9 1 25 7 8 3 2 4 5 27 19 18 17 21 22 20 10 d1 r10 2.00k r12 4.02k r11 1.50k ntc1 10k b = 3380 thrm vcc_sense vss_sense load-line adjustment : r fb = r droop /(r sense x 600 s) dcr thermal compensa tion pwr pwr pwr agnd ilim 26 r2 11.4k v alley current limit set by time to ilim v limit = 0.2v x r1/(r2 + r1) slew ra te set by time bias current dv/dt = 12.5mv/ s x 71.5k /(r2 + r1) core output gnd (ep) agnd agnd stdby 16 dprslpvr 6 24 ccv 28 agnd agnd agnd d0 d1 d2 d3 d4 vid inputs 11 12 13 14 15 vrhot remote-sense inputs remote-sense filters switching frequency (f sw = 1/t sw ): t sw = 16.3pf x (r ton + 6.5k ) r16 10 r15 10 ca tch resistors required when cpu not popula ted agnd r gnd 0 c ccv 100pf c9 1000pf r fb 8.25k 1% r13 10 pwr 29 r4 open agnd c in pwr MAX8797 gnd 23 pwr r vrhot 10k agnd c csp open c bst 0.1 f r bst 0 r ton 200k agnd c vcc 1.0 f c vdd 1.0 f r vcc 10 c sense 0.22 f agnd c csn open c10 1000pf r14 10 input 7v to 24v 5v bias input figure 2. MAX8797 gmch application circuit
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 24 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees detailed description free-running, constant on-time controllers with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time, current-mode regulator with voltage feed-forward (figure 3). this architecture relies on the output filter capacitors esr and the load regulation to provide the proper current-mode compen- sation, so the resulting feedback ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely b y a one-shot whose period is inversely proportional to input voltage, and directly proportional to the feedback volt- age (see the on-time one-shot section). another one- shot sets a minimum off-time. the on-time one-shot triggers when the error comparator goes low (the feed- back voltage drops below the target voltage), the inductor current is below the valley current-limit thresh- old, and the minimum off-time one-shot times out. design parameters crestline cantiga input voltage range 7v to 20v 7v to 20v maximum load current 8a (10a ocp) 10a (12a ocp) transient load current 7a (5a/s) 8a (5a/s) load line 7.8mv/a 7.5mv/a components ton resistance (r ton ) 200k (f sw = 300khz) 200k (f sw = 300khz) inductance (l) nec/tokin mpc0750lr60 0.56h, 17a, 2.30m nec/tokin mpc0750lr60 0.56h, 17a, 2.30m high-side mosfet (n h ) fairchild fds8690 8.6m /11.4m (typ/max) fairchild fds8690 8.6m /11.4m (typ/max) low-side mosfet (n l ) fairchild fds8660s 2.6m /3.5m (typ/max) fairchild fds8660s 2.6m /3.5m (typ/max) output cap (c out ) 2x 330f, 12m , 2.5v sanyo 2r5tpe330mcc2 6x 10f, 6v ceramic (0805) 2x 330f, 12m , 2.5v sanyo 2r5tpe330mcc2 6x 10f, 6v ceramic (0805) input cap (c in ) 2x 10f, 25v ceramic (1210) 2x 10f, 25v ceramic (1210) time/ilim resistance (r1) 7.15k 8.06k ilim/gnd resistance (r2) 61.9k 61.9k fb resistance (r fb ) 8.25k 8.25k lx/csp resistance (r10) 2.00k 2.00k csp/csn series resistance (r11) 1.50k 1.50k parallel ntc resistance (r12) 4.02k 4.02k dcr sense ntc (ntc1) 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f dcr sense capacitance (c sense ) 0.1f, 6v ceramic (0603) 0.1f, 6v ceramic (0603) table 2. gmch component selection
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 25 confidential information?estricted to intel imvp-6 licensees s r q r s q trig q one-shot pgnd dl bst dh lx ccv ref ton csp csn minimum off-time pwrgd t arget + 200mv t arget - 300mv t arget + 300mv target - 400mv shdn trig q one-shot on-time mode control fb dprstp dprslpvr v dd fb pgnd lx 1mv skip csp csn d0?6 clken gnds 60 s startup delay 5ms startup delay dac current scaling time fault target ref v3p3 (gmch) stdby 3% offset gmch ilim r f aul t blank vcc gnd ref (2.0v) 500k g m(ccv) 160 s g m(fb) 600 s g m(gnds) slew_rate pgdin pwr power monitor csn-gnds vrhot thrm 0.3 x v cc max8796 MAX8797 max17401 10x figure 3. functional diagram
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 26 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees +5v bias supply (v cc and v dd ) the quick-pwm controller requires an external +5v bias supply in addition to the battery. typically, this +5v bias supply is the notebooks 95%-efficient, +5v system sup- ply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v bias supply can be gen- erated with an external linear regulator. the +5v bias supply must provide v cc (pwm con- troller) and v dd (gate-drive power), so the maximum current drawn is: where i cc is provided in the electrical characteristics table, f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheets total gate- charge specification limits at v gs = 5v. v in and v dd can be connected if the input power source is a fixed +4.5v to +5.5v supply. if the +5v bias supply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. switching frequency (ton) connect a resistor (r ton ) between ton and v in to set the switching period (t sw = 1/f sw ): t sw = 16.3pf x (r ton + 6.5k ) a 96.75k to 303.25k corresponds to switching peri- ods of 1.67s (600khz) to 5s (200khz), respectively. high-frequency (over 500khz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low-frequency (under 300khz) operation offers the best overall efficiency at the expense of component size and board space. ton open-circuit fault protection the ton input includes open-circuit protection to avoid long, uncontrolled on-times that could result in an over- voltage condition on the output. the max8796/ MAX8797/max17401 detect an open-circuit fault if the ton current drops below 10a for any reasonthe ton resistor (r ton ) is unpopulated, a high resistance value is used, the input voltage is low, etc. under these conditions, the max8796/MAX8797/max17401 stop switching (dh and dl pulled low) and immediately set the fault latch. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. on-time one-shot the core contains a fast, low-jitter, adjustable one-shot that sets the high-side mosfets on-time. the one-shot varies the on-time in response to the input and feedback voltages. the main high-side switch on-time is inversely proportional to the input voltage as measured by the r ton input, and proportional to the feedback voltage (v fb ): where the switching period (t sw = 1/f sw ) is set by the resistor between v in and ton. this algorithm results in a nearly constant switching fre- quency despite the lack of a fixed-frequency clock gen- erator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the on-time one-shots have good accuracy at the operating points specified in the electrical characteristics table. on-times at operating points far removed from the conditions specified in the electrical characteristics table can vary over a wider range. on-times translate only roughly to switching frequen- cies. the on-times guaranteed in the electrical characteristics table are influenced by switching delays in the external high-side mosfet. resistive losses, including the inductor, both mosfets, and printed-circuit board (pcb) copper losses in the output and ground tend to raise the switching frequency as the load current increases. under light-load conditions, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only during forced-pwm operation and dynamic output-voltage transitions when the inductor current reverses at light- or negative-load currents. with reversed inductor cur- rent, the inductors emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: where v dis is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rec- tifier, inductor, and pcb resistances; v chg is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and pcb resis- tances; and t on is the on-time as determined above. f vv tv v v sw out dis on in dis chg = + () +? () tt v v on s w fb in = ? ? ? ? ? ? ii f q q bias cc sw g low g high =+ + () () ( )
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 27 confidential informa tion?estricted to intel imvp-6 licensees current sense the output current is differentially sensed by the high- impedance current-sense inputs (csp and csn). low- offset amplifiers are used for voltage-positioning gain, current-limit protection, and power monitoring. sensing the current at the output offers advantages, including less noise sensitivity and the flexibility to use either a current-sense resistor or the dc resistance of the power inductor. using the dc resistance (r dcr ) of the inductor allows higher efficiency. in this configuration, the initial toler- ance and temperature coefficient of the inductors dcr must be accounted for in the output-voltage droop-error budget and power monitor. this current-sense method uses an rc filtering network to extract the current infor- mation from the inductor (see figure 4). the resistive divider used should provide a current-sense resistance (r cs ) low enough to meet the current-limit requirements (r cs x i out(max) < 50mv), and the time constant of the rc network should match the inductors time constant (l/r dcr ): and: where r cs is the required current-sense resistance, and r dcr is the inductors series dc resistance. use the worst-case inductance and r dcr values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. to mini- mize the current-sense error due to the current-sense inputs bias current (i csp ), choose r1 || r2 to be less than 2k and use the above equation to determine the sense capacitance (c eq ). choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. temperature compensation is recommended for this current-sense method. see the voltage positioning and loop compensation section for detailed information. when using a current-sense resistor for accurate output- voltage positioning, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current-sense resistor (see figure 4). the esl-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error r l cr r dcr eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + ? ? ? ? ? ? 2 12 a) output series resistor sensing dh_ input (v in ) dl_ lx_ pgnd n h c in l esl r sense r sense l sense c eq c out c eq r1 = d l csp_ csn_ l sense resistor r1 r1 + r2 r2 r cs = ( ) [ + ] r dcr c eq l r dcr = r1 1 r2 1 for thermal compensa tion: r2 should consist of an ntc resistor in series with a st andard thin-film resistor. n l b) lossless inductor sensing dh_ input (v in ) dl_ lx_ pgnd n h c in l dcr c eq c out d l csp_ csn_ inductor r1 n l r2 figure 4. current-sense methods
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 28 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees that results in unwanted offsets in the regulation voltage and results in early current-limit detection. similar to the inductor dcr sensing method, the rc filters time con- stant should match the l/r time constant formed by the current-sense resistors parasitic inductance: where l esl is the equivalent series inductance of the current-sense resistor, r sense is the current-sense resistance value, c eq and r1 are the time-constant matching components. current limit the current-limit circuit employs a valley current-sens- ing algorithm that uses a current-sense element (see figure 4) between the current-sense inputs (csp to csn) to detect the inductor current. if the differential current-sense voltage exceeds the current-limit thresh- old, the pwm controller does not initiate a new cycle until the inductor current drops below the valley current- limit threshold. since only the valley current level is actively limited, the actual peak inductor current exceeds the valley current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense impedance, inductor value, and battery voltage. when combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. the positive valley current-limit threshold voltage at csp to csn equals precisely 1/10 of the differential time to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). connect ilim directly to v cc to set the default current-limit threshold setting of 22.5mv nominal for imvp-6 (max8796/max17401: v3p3 = 3.3v) and 17.5mv nominal for gmch (MAX8797 and max8796/max17401: v3p3 = gnd). the negative current-limit threshold (forced-pwm mode only) is nominally -125% of the corresponding valley current-limit threshold. when the inductor current drops below the negative current limit, the controller immedi- ately activates an on-time pulsedl turns off, and dh turns onallowing the inductor current to remain above the negative current threshold. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signals seen by the current-sense inputs (csp, csn). feedback the nominal no-load output voltage (v target ) is defined by the vid-selected dac voltage (see tables 3 and 4) plus the remote ground-sense adjustment (v gnds ) as defined in the following equation: where v dac is the selected vid voltage. on startup, imvp-6 (max8796/max17401: v3p3 = 3.3v) applica- tions slew the target voltage from ground to the preset boot voltage and gmch (MAX8797 or max8796/ max17401: v3p3 = gnd) applications slew the target voltage directly to the vid-selected dac target. voltage-positioning amplifier (steady-state droop) the max8796/MAX8797/max17401 include a transcon- ductance amplifier for adding gain to the voltage-posi- tioning sense path. the amplifiers input is generated by the differential current-sense inputs, which sense the inductor current by measuring the voltage across either current-sense resistors or the inductors dcr. the amplifiers output connects directly to the regulators voltage-positioned feedback input (fb), so the resis- tance between fb and the output-voltage sense point determines the voltage-positioning gain: where the target voltage (v target = v fb ) is defined by the selected vid code (table 3 for imvp6 or table 4 for gmch), and the fb amplifiers output current (i fb ) is determined by the sum of the current-sense voltages: where g m(fb) is typically 600s as defined in the electrical characteristics table. differential remote sense the max8796/MAX8797/max17401 include differential, remote-sense inputs to eliminate the effects of voltage drops along the pcb traces and through the proces- sors power pins. the feedback-sense node connects to the voltage-positioning resistor (r fb ). the ground- sense (gnds) input connects to an amplifier that adds an offset directly to the feedback voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. connect the voltage-position- ing resistor (r fb ) and ground-sense (gnds) input directly to the processors remote-sense outputs as shown in figures 1 and 2. ig v v fb m fb csp csn =? () () vv r i out target fb fb =? vv v v target fb dac gnds == + l r cr esl sense eq = 1
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 29 confidential informa tion?estricted to intel imvp-6 licensees integrator amplifier an integrator amplifier forces the dc average of the fb voltage to equal the target voltage. this transconduc- tance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (figure 3), allowing accurate dc output-voltage regula- tion regardless of the output ripple voltage. the integra- tor amplifier has the ability to shift the output voltage by 50mv (typ). the integration time constant can be set easily with an external compensation capacitor between ccv and analog ground, with the minimum recommended ccv capacitor value determined by: c ccv >> g m(ccv) /(16 x f sw ) where g m(ccv) = 320s (max) is the integrators transconductance and f sw is the switching frequency set by the r ton resistance. the max8796/MAX8797/max17401 disable the inte- grator by connecting the amplifier inputs together at the beginning of all downward vid transitions done in pulse-skipping mode (dprslpvr = high). the integra- tor remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). dac inputs (d0?6) the digital-to-analog converter (dac) programs the output voltage using the d0Cd6 inputs. d0Cd6 are low- voltage (1.0v) logic inputs designed to interface direct- ly with the cpu. do not leave d0Cd6 unconnected. changing d0Cd6 initiates a transition to a new output- voltage level. change d0Cd6 together, avoiding greater than 20ns skew between bits. otherwise, incorrect dac readings can cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. the available dac codes and resulting output voltages are compatible with the intel imvp-6 (table 3) and intel gmch specifications (table 4). d6 d5 d4 d3 d2 d1 d0 imvp-6 output voltage (v) d6 d5 d4 d3 d2 d1 d0 imvp-6 output voltage (v) 0 0 0 0 0 0 0 1.5000 1 0 00000 0.7000 0 0 0 0 0 0 1 1.4875 1 0 00001 0.6875 0 0 0 0 0 1 0 1.4750 1 0 00010 0.6750 0 0 0 0 0 1 1 1.4625 1 0 00011 0.6625 0 0 0 0 1 0 0 1.4500 1 0 00100 0.6500 0 0 0 0 1 0 1 1.4375 1 0 00101 0.6375 0 0 0 0 1 1 0 1.4250 1 0 00110 0.6250 0 0 0 0 1 1 1 1.4125 1 0 00111 0.6125 0 0 0 1 0 0 0 1.4000 1 0 01000 0.6000 0 0 0 1 0 0 1 1.3875 1 0 01001 0.5875 0 0 0 1 0 1 0 1.3750 1 0 01010 0.5750 0 0 0 1 0 1 1 1.3625 1 0 01011 0.5625 0 0 0 1 1 0 0 1.3500 1 0 01100 0.5500 0 0 0 1 1 0 1 1.3375 1 0 01101 0.5375 0 0 0 1 1 1 0 1.3250 1 0 01110 0.5250 0 0 0 1 1 1 1 1.3125 1 0 01111 0.5125 0 0 1 0 0 0 0 1.3000 1 0 10000 0.5000 0 0 1 0 0 0 1 1.2875 1 0 10001 0.4875 0 0 1 0 0 1 0 1.2750 1 0 10010 0.4750 0 0 1 0 0 1 1 1.2625 1 0 10011 0.4625 0 0 1 0 1 0 0 1.2500 1 0 10100 0.4500 table 3. imvp-6 output voltage vid dac codes (max8796/max17401 v3p3 = 3.3v)
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 30 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees d6 d5 d4 d3 d2 d1 d0 imvp-6 output voltage (v) d6 d5 d4 d3 d2 d1 d0 imvp-6 output voltage (v) 0 0 1 0 1 0 1 1.2375 1 0 10101 0.4375 0 0 1 0 1 1 0 1.2250 1 0 10110 0.4250 0 0 1 0 1 1 1 1.2125 1 0 10111 0.4125 0 0 1 1 0 0 0 1.2000 1 0 11000 0.4000 0 0 1 1 0 0 1 1.1875 1 0 11001 0.3875 0 0 1 1 0 1 0 1.1750 1 0 11010 0.3750 0 0 1 1 0 1 1 1.1625 1 0 11011 0.3625 0 0 1 1 1 0 0 1.1500 1 0 11100 0.3500 0 0 1 1 1 0 1 1.1375 1 0 11101 0.3375 0 0 1 1 1 1 0 1.1250 1 0 11110 0.3250 0 0 1 1 1 1 1 1.1125 1 0 11111 0.3125 0 1 0 0 0 0 0 1.1000 1 1 00000 0.3000 0 1 0 0 0 0 1 1.0875 1 1 00001 0.2875 0 1 0 0 0 1 0 1.0750 1 1 00010 0.2750 0 1 0 0 0 1 1 1.0625 1 1 00011 0.2625 0 1 0 0 1 0 0 1.0500 1 1 00100 0.2500 0 1 0 0 1 0 1 1.0375 1 1 00101 0.2375 0 1 0 0 1 1 0 1.0250 1 1 00110 0.2250 0 1 0 0 1 1 1 1.0125 1 1 00111 0.2125 0 1 0 1 0 0 0 1.0000 1 1 01000 0.2000 0 1 0 1 0 0 1 0.9875 1 1 01001 0.1875 0 1 0 1 0 1 0 0.9750 1 1 01010 0.1750 0 1 0 1 0 1 1 0.9625 1 1 01011 0.1625 0 1 0 1 1 0 0 0.9500 1 1 01100 0.1500 0 1 0 1 1 0 1 0.9375 1 1 01101 0.1375 0 1 0 1 1 1 0 0.9250 1 1 01110 0.1250 0 1 0 1 1 1 1 0.9125 1 1 01111 0.1125 0 1 1 0 0 0 0 0.9000 1 1 10000 0.1000 0 1 1 0 0 0 1 0.8875 1 1 10001 0.0875 0 1 1 0 0 1 0 0.8750 1 1 10010 0.0750 0 1 1 0 0 1 1 0.8625 1 1 10011 0.0625 0 1 1 0 1 0 0 0.8500 1 1 10100 0.0500 0 1 1 0 1 0 1 0.8375 1 1 10101 0.0375 0 1 1 0 1 1 0 0.8250 1 1 10110 0.0250 0 1 1 0 1 1 1 0.8125 1 1 10111 0.0125 0 1 1 1 0 0 0 0.8000 1 1 11000 0 0 1 1 1 0 0 1 0.7875 1 1 11001 0 0 1 1 1 0 1 0 0.7750 1 1 11010 0 table 3. imvp-6 output voltage vid dac codes (max8796/max17401 v3p3 = 3.3v) (continued)
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 31 confidential informa tion?estricted to intel imvp-6 licensees output-voltage transition timing the max8796/MAX8797/max17401 perform mode transitions in a controlled manner, automatically mini- mizing input surge currents. this feature allows the cir- cuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output volt- age level with the lowest possible peak currents for a given output capacitance. at the beginning of an output-voltage transition, the max8796/MAX8797/max17401 blank both pwrgd thresholds, preventing the pwrgd open-drain output and the clken push-pull output from changing states during the transition. the controller reenables the lower pwrgd threshold approximately 20s after the slew- rate controller reaches the target output voltage. the controller reenables the upper pwrgd threshold 20s after the slew-rate controller reaches the target output voltage only for upward vid transitions. for downward vid transitions, the max8796/MAX8797/max17401 must also detect an error amplifier transition (feedback drops below the new target threshold) before reen- abling the upper pwrgd transition to avoid false pwrgd errors under pulse-skipping conditions. the slew rate (set by resistor r time ) must be set fast enough to ensure that the transition can be completed within the maximum allotted time. d4 d3 d2 d1 d0 gmch output voltage (v) d4 d3 d2 d1 d0 gmch output voltage (v) 0 0 0 0 0 1.28750 1 0 0 0 0 0.87750 0 0 0 0 1 1.26175 1 0 0 0 1 0.84975 0 0 0 1 0 1.23600 1 0 0 1 0 0.82400 0 0 0 1 1 1.21025 1 0 0 1 1 0.79825 0 0 1 0 0 1.18450 1 0 1 0 0 0.77250 0 0 1 0 1 1.15875 1 0 1 0 1 0.74675 0 0 1 1 0 1.13300 1 0 1 1 0 0.72100 0 0 1 1 1 1.10725 1 0 1 1 1 0.69525 0 1 0 0 0 1.08150 1 1 0 0 0 0.66950 0 1 0 0 1 1.05575 1 1 0 0 1 0.64375 0 1 0 1 0 1.03000 1 1 0 1 0 0.61800 0 1 0 1 1 1.00425 1 1 0 1 1 0.59225 0 1 1 0 0 0.97850 1 1 1 0 0 0.56650 0 1 1 0 1 0.95275 1 1 1 0 1 0.54075 0 1 1 1 0 0.92700 1 1 1 1 0 0.51500 0 1 1 1 1 0.90125 1 1 1 1 1 0.41200 d6 d5 d4 d3 d2 d1 d0 imvp-6 output voltage (v) d6 d5 d4 d3 d2 d1 d0 imvp-6 output voltage (v) 0 1 1 1 0 1 1 0.7625 1 1 11011 0 0 1 1 1 1 0 0 0.7500 1 1 11100 0 0 1 1 1 1 0 1 0.7375 1 1 11101 0 0 1 1 1 1 1 0 0.7250 1 1 11110 0 0 1 1 1 1 1 1 0.7125 1 1 11111 0 table 3. imvp-6 output voltage vid dac codes (max8796/max17401 v3p3 = 3.3v) (continued) table 4. gmch output voltage vid dac codes (MAX8797 or max8796/max17401 when v3p3 = gnd)
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 32 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees the max8796/MAX8797/max17401 automatically con- trol the current to the minimum level required to com- plete the transition in the calculated time. the slew-rate controller uses an internal capacitor and current-source programmed by r time to transition the output voltage. the total transition time depends on r time , the voltage difference, and the accuracy of the slew-rate controller (c slew accuracy). the slew rate is not dependent on the total output capacitance, as long as the surge cur- rent is less than the current limit. for all dynamic vid transitions, the transition time (t tran ) is given by: where dv target /dt = 12.5mv/s x 71.5k /r time is the slew rate, v old is the original output voltage, and v new is the new target voltage. see time slew-rate accuracy in the electrical characteristics table for slew- rate limits. for soft-start and shutdown, the controller automatically reduces the slew rate to 1/8. the output voltage tracks the slewed target voltage, making the transitions relatively smooth. excluding the load current, the average inductor current required to make an output voltage transition is: where dv target /dt is the required slew rate and c out is the total output capacitance. imvp-6 deeper sleep transitions when dprslpvr goes high, the max8796/max17401 immediately enter pulse-skipping operation (see figures 5, 6, 7). if the vids are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. the internal target still ramps as before, and the upper pwrgd threshold remains blanked high impedance until the output volt- age reaches the internal target: fast c4e deeper sleep exit: when exiting deeper sleep (dprslpvr pulled low) while the output volt- age still exceeds the deeper sleep voltage, the max8796/max17401 quickly slew (50mv/s min regardless of r time setting) the internal target volt- age to the dac code provided by the processor as long as the output voltage is above the new target. the controller remains in skip mode until the output voltage equals the internal target (until the first on- time is triggered by the error amplifier). once the internal target reaches the output voltage, switching begins and the controller is allowed to enter forced- pwm mode. the controller blanks pwrgd and clken (forced high impedance) until 20s after the transition is completed. see figure 5. i c dv dt l out target ? () / t vv dv dt tran new old target = ? () / dprslpvr pwrgd t blank 20 s typ t blank 20 s typ dh1 cpu core vol t age internal t arget actual v out vid (d0?6) clken no pulses: v out > v target blank high threshold only blank high threshold onl y dprstp internal pwm mode forced-pwm mode ovp set to 1.75v min active vid lfm vid dprslp vid ovp level ovp level ovp tracks internal target blank lo blank low blank high-z blank high-z pulse-skipping mode deeper sleep vid figure 5. imvp-6 c4e (c4 early exit) transition
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 33 confidential informa tion?estricted to intel imvp-6 licensees standard c4 deeper sleep exit: when exiting deeper sleep (dprslpvr pulled low) while the out- put voltage is regulating to the deeper sleep volt- age, the max8796/max17401 immediately ramp the output voltage to the lfm dac code provided by the processor at the slew rate set by r time . the controller blanks pwrgd and clken (forced high impedance) until 20s after the transition is com- pleted. see figure 6. slow c4 deeper sleep exit: when exiting deeper sleep (dprslpvr stays high, dprstp pulled high) while the output voltage is regulating to the deeper sleep voltage, the max8796/max17401 remain in skip mode and ramp the output voltage to the lfm dac code provided by the processor at 1/4 the slew rate set by r time . the controller blanks pwrgd and clken (forced high impedance) until 20s after the transition is completed. see figure 7. blank low dprslpvr pwrgd t blank 20 s typ t blank 20 s typ internal pwm mode blank high-z dh cpu core vol t age internal t arget actual v out vid (d0?6) clken active vid lfm vid dprslp vid dprstp ovp level ovp level blank high threshold only blank low blank high-z no pulses: v out > v t arget pulse-skipping mode deeper sleep vid forced-pwm mode lfm vid ovp set to 1.75v min ovp tracks internal t arget figure 6. standard imvp-6 c4 transition
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 34 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees gmch sleep transition for gmch applicationsthe max8796/max17401 (v3p3 = gnd) or MAX8797the system enters the sleep state by selecting a lower vid dac code. when dprslpvr is forced high (for the best light-load effi- ciency), the controller operates in a pulse-skipping mode and passively transitions to the lower sleep volt- age. once the vids are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance while the internal target ramps down at the slew rate set by r time . the upper pwrgd threshold remains blanked high impedance until the output voltage reaches the internal target: standard gmch sleep exit: when exiting the sleep state while the output voltage is regulating to the selected sleep vid voltage, the controller imme- diately ramps the output voltage to the newly selected active vid code at the slew rate set by r time . the controller blanks pwrgd (forced high impedance) until 20s after the transition is com- pleted. see figure 8. early gmch sleep exit: when exiting the sleep state while the output voltage still exceeds the inter- nal target (the sleep voltage), the controller quickly slews (50mv/s min regardless of r time setting) the internal target voltage to the new vid dac code as long as the output voltage exceeds the new tar- get. once the internal target reaches the output voltage, switching begins and the controller contin- ues to ramp up the internal target and output volt- age at the slew rate selected by r time . the controller blanks pwrgd (forced high impedance) until 20s after the transition is completed. see figure 9. blank low dprslpvr pwrgd t blank 20 s typ t blank 20 s typ slow slew ra te internal pwm mode blank high-z dh cpu core vol t age internal t arget actual v out vid (d0?6) clken active vid lfm vid dprslp vid dprstp ovp level ovp level deeper sleep vid ovp set to 1.75v min ovp tracks internal target blank low blank high-z forced-pwm mode pulse-skipping mode lfm vid no pulses: v out > v t arget blank high threshold only figure 7. imvp-6 slow c4 transition
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 35 confidential information?estricted to intel imvp-6 licensees pwrgd dprslpvr = 3.3v or 5v gmch: MAX8797 or max8796/max17401 (v3p3 = gnd) t blank 20 s typ t blank 20 s typ blank high-z dh cpu core vol t age internal t arget blank high threshold only sleep vid active vid ovp level ovp level ovp set to 1.50v min actual v out active vid blank high-z vid (d0?5) sleep vid active vid ovp tracks internal target no pulses: v out > v target figure 8. standard gmch sleep transition pwrgd dprslpvr = 3.3v or 5v gmch: MAX8797 or max8796/max17401 (v3p3 = gnd) t blank 20 s typ t blank 20 s typ blank high-z dh1 cpu core vol t age internal t arget blank high threshold only no pulses: v out > v t arget sleep vid active vid ovp level ovp level ovp set to 1.50v min ovp tracks internal target actual v out active vid vid (d0?5) deeper sleep vid blank high-z figure 9. early exit gmch sleep transition
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 36 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees forced-pwm operation (normal mode) during soft-shutdown and normal operationwhen the cpu is actively running (dprslpvr = low, table 5) the max8796/MAX8797/max17401 operate with the low-noise, forced-pwm control scheme. forced-pwm operation disables the zero-crossing comparator, forc- ing the low-side gate-drive waveforms to constantly be the complement of the high-side gate-drive waveforms. this keeps the switching frequency constant and allows the inductor current to reverse under light loads, pro- viding fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load +5v bias supply current remains between 10ma to 50ma, depending on the external mosfets and switching fre- quency. to maintain high efficiency under light-load con- ditions, the processor can switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. the max8796/MAX8797/max17401 automatically use pulse-skipping operation during soft- start, regardless of the dprslpvr configuration. light-load pulse-skipping operation (deeper sleep) during soft-start and sleep statesdprslpvr is pulled highthe max8796/MAX8797/max17401 operate in pulse-skipping mode. the pulse-skipping mode enables the drivers zero-crossing comparator, so the controller pulls dl low when the low-side mosfet volt- age drop (lx to gnd voltage) detects zero inductor current. this keeps the inductor from sinking current and discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. upon entering pulse-skipping operation, the controller temporarily blanks the upper pwrgd and clken thresholds, and sets the transitional ovp threshold to 300mv above the maximum vid voltage allowed 1.80v for imvp-6 and 1.55v for gmchto prevent false ovp faults when the transition to pulse-skipping operation coincides with a vid code change. once the error amplifier detects that the output voltage is in regu- lation, the upper pwrgd, upper clken , and ovp thresholds resume tracking the selected vid dac code. the max8796/MAX8797/max17401 automatical- ly use forced-pwm operation during soft-shutdown, regardless of the dprslpvr configuration. automatic pulse-skipping switchover in skip mode (dprslpvr = high), an inherent automatic switchover to pfm takes place at light loads (figure 10). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the zero-crossing comparator senses the inductor current across the low-side mosfets. once v lx drops below the zero-crossing comparator threshold (see the electrical characteristics table), the comparator forces dl low (figure 3). this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current opera- tion. the pfm/pwm crossover occurs when the load-cur- rent is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 10). for a bat- tery input range of 7v to 20v, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. the total load current at the pfm/pwm crossover threshold (i load(skip) ) is approximately: the switching waveforms might appear noisy and asyn- chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs between pfm noise and light-load efficiency are made by vary- ing the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input-voltage levels. i tv l vv v lo a d s k i p sw o u t i n o u t in () = ? ? ? ? ? ? ? ? ? ? ? ? ? inductor current i load = i peak / 2 on-time 0 time i peak l v batt - v out i t = figure 10. pulse-skipping/discontinuous crossover point
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 37 confidential information?estricted to intel imvp-6 licensees s hdn dp rs t p (imvp-6 only) dprslpvr operating mode gnd x x disabled l o w - p o w e r s hutd o w n. dl for ced l o w , a n d the c o n tr o l l e r i s d i s a b l ed . the s u p p l y cur r ent d r o p s b e l o w 3 a ( 1a m a x p e r s u p p l y p i n ) . r i s i n g x x pu l s e s k i pp i n g 1/ 8 r ti me sl e w ra t e s t art u p : w h e n s hdn i s p u l l e d h i g h , th e ma x 8 796 /ma x 879 7/ ma x 1 7 401 b e g i n t h e s t a r t u p s e q u e nce a f te r t h e i n te r n al ci r cui t r y p o w e r s u p . t h e ma x 8 796 /ma x 87 97 /ma x 1 740 1 ena b l e th e p w m co ntr o l l e r a n d r a mp the o u tp ut v o l t ag e up to t h e s t ar tup v o l t ag e. s e e fi g u r e s 11 a n d 12 . hi gh x l o w for ced - p w m n o m i nal r ti me s l ew r a te fu l l p o w e r : t h e no- l oad o u tp ut v o l t ag e i s d e t e r m i n ed b y t h e s e l e c t ed v i d da c cod e ( tab l e s 3 a n d 4) . hig h l o w hi g h pu l s e - s k i pp i n g n o m i nal r ti me s l ew r a te d eepe r s l e ep m o d e : the no - l oa d ou t p ut v o l t a g e i s d e te r m i n e d b y the s e l ecte d v i d d a c co d e ( t a b l e s 3 an d 4 ) . w hen d p r s l p v r i s p u l l e d h i g h , the cont r o l l e r i m me d i ate l y ente r s 1 - p h a s e p u l s e - s k i p p i n g o p e r a t i on, a l l o w i n g automat i c p w m/ p f m s w i t cho v e r un d e r l i g h t l o a d s . the p w r g d an d cl k e n up p e r t h r e s h o l d s ar e b l a n k e d d u r i ng t h e tr an s i t i o n . high hi g h hi g h pu l s e - s k i pp i n g 1/ 4 r ti me sl e w ra t e d eepe r s l eep s l o w exi t m o d e ( i m vp- 6 o n l y) . t h e n o - l o a d o u t p u t v o l t ag e i s d e t e r m i n ed b y t h e s e l e c t ed v i d da c c o d e ( tab l e 3) . w hen dp r s t p is p u ll e d h i g h w h il e d p r s l p v r is a l r e a d y h i g h , t h e m a x 8 79 6/ m a x 1 7 4 0 1 r e ma i n s i n p u l s e- s k i p p i n g op e r at i o n, a l l o w i ng au to m a t i c p w m/p fm s w i t c h o v er u n d e r l i g h t l o ad s . th e p w r g d and cl k e n t h r e s h o l d s ar e b l an k e d d u r i ng th e tr an s i t i o n . falli ng x x for ced - p w m 1/ 8 r ti me sl e w ra t e s h u t d o w n . w hen s hdn i s p u l l e d l o w , t h e ma x 8 796 /ma x 8 7 9 7 / ma x 17 401 i mme d i atel y p u l l p w r g d l o w , cl k e n b e comes h i g h i m p e d anc e, a n d th e ou tp ut v o l t ag e i s r a mp ed d o w n t o g r ound . o nce th e ou tp ut r eac he s z e r o , th e c o n t r o l l e r e n t e r s th e l o w - p o w e r s h utd ow n s t ate . s e e f i g u r e s 1 1 an d 1 2 . high x x disabl ed f a u l t mo d e . the fa u l t l a t c h ha s b e e n s e t b y t h e m a x 8 79 6/ ma x 8 7 9 7 / ma x 1 740 1 u v p f a ul t, r to n op en fa u l t , or ther ma l - s h utd ow n p r o t e c t i on an d ma x 87 96 / ma x 8 797 o v p f a ul t. th e con t r ol l e r r e mai n s i n fa u l t mo d e un t i l v cc p o w e r i s cy cl e d o r s hdn tog g l ed . table 5. operating mode truth table power-up sequence (por, uvlo) the max8796/MAX8797/max17401 are enabled when shdn is driven high (figures 11 and 12). the internal reference powers up first, followed by the analog con- trol circuitry. roughly 50s after the analog control cir- cuitry powers up, the pwm controller is enabled and begins the soft-start sequence. power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar- ing the controller for operation. the v cc uvlo circuitry inhibits switching until v cc rises above 4.25v. the con- troller powers up the reference once the system enables the controller, v cc is above 4.25v, and shdn is driven high. the soft-start sequence ramps the out- put voltage up to the target voltageeither the 1.20v boot voltage for imvp-6 or the selected vid voltage for gmchat 1/8 the nominal slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k < /r time is the nominal slew rate. the soft-start circuitry does not use a variable current limit, so full output current is available immediately. the max8796/MAX8797/max17401 auto- matically use pulse-skipping mode during soft-start and use forced-pwm mode during soft-shutdown, regard- less of the dprslpvr configuration. t v dv dt tran start start target () / = () 8
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 38 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees for imvp-6 applications (max8796/max17401 with v3p3 = 3.3v), the max8796/max17401 pull clken low approximately 60s after reaching the boot voltage. at the same time, the max8796/max17401 slew the out- put to the selected vid voltage at the programmed nominal slew rate. pwrgd becomes high impedance approximately 5ms after clken is pulled low. for gmch applications (MAX8797 or max8796/ max17401 with v3p3 = gnd), pwrgd becomes high impedance approximately 60s after reaching the select- ed vid voltage. for automatic startup, the battery voltage should be present before v cc rises above its uvlo threshold. if the controller attempts to bring the output into regula- tion without the battery voltage present, the output undervoltage fault latch disables the controller. the max8796/MAX8797/max17401 remain shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 0.5v. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage to make valid decisions. to protect the output from over- voltage faults, the controller shuts down immediately and forces a high-impedance output (dl and dh pulled low) and pulls csn low through a 10 discharge mosfet. shdn pwrgd v cc soft -st ar t 1/8 r time slew ra te soft -shutdown 1/8 r time slew ra te clken vid (d0?6) valid vid inv alid vid cpu core vol t age internal pwm mode forced-pwm mode pulse skipping ovp tracks internal target ovp set to 1.75v min ovp level ovp set to 1.75v min invalid vid 1.2v boot t blank 20 s typ t blank 60 s typ t blank 5ms typ t blank 60 s typ figure 11. imvp-6 power-up and shutdown sequence timing diagram
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 39 confidential informa tion?estricted to intel imvp-6 licensees shutdown when shdn goes low, the max8796 / MAX8797/ max17401 enter low-power shutdown mode. pwrgd is pulled low immediately, and the output voltage ramps down at 1/8 the slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k /r time is the nominal slew rate. slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excursion that occurs when the con- troller discharges the output quickly by permanently turning on the low-side mosfet (underdamped response). this eliminates the need for the schottky diode connected between the output and ground to clamp the negative output-voltage excursion. after the controller reaches the zero target, the max8796/ MAX8797/max17401 shut down completelythe dri- vers are disabled (dl and dh are pulled low)the internal reference turns off, and the supply currents drop to about 1a (max). when an output undervoltage fault condition activates the shutdown sequence, the protection circuitry sets the uvp fault latch to prevent the controller from restarting. to clear the fault latch and reactivate the controller, toggle shdn or cycle v cc power below 0.5v. power monitor (pwr) the max8796/MAX8797/max17401 include a single- quadrant multiplier used to determine the actual output power based on the inductor current (the differential cs input) and output voltage (csn to gnds). the buffered output of this multiplier is connected to pwr and pro- vides a voltage relative to the output power dissipation: where v csp - v csn = i load x r sense , and the power- monitor scale factor (k pwr ) is typically 25. the power monitor allows the system to accurately monitor the cpus power dissipation and quickly predict if the sys- tem is about to overheat before the significantly slower temperature sensor signals an overtemperature alert. v kv v v v vv pwr pwr csn gnds csp csn time ilim = ? () ? () ? () t v dv dt tran shdn out target () / = () 8 shdn pwrgd v cc soft -st ar t 1/8 r time slew ra te soft -shutdown 1/8 r time slew ra te vid (d0?5) v alid vid gmch core vol t age internal pwm mode forced-pwm pulse skipping ovp tracks internal target ovp set to 1.50v min ovp level ovp set to 1.50v min invalid vid t blank 60 s typ t blank 60 s typ figure 12. gmch power-up and shutdown sequence timing diagram
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 40 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees temperature comparator (vrhot) the max8796/MAX8797/max17401 also feature an inde- pendent comparator with an accurate threshold that tracks the analog supply voltage (v hot = 0.3 x v cc ). this makes the thermal trip threshold independent of the v cc supply voltage tolerance. use a resistor- and thermistor- divider between v cc and gnd to generate a voltage- regulator overtemperature monitor. place the thermistor as close to the mosfets and inductors as possible. fault protection (latched) output overvoltage protection (ovp) (max8796/MAX8797 only) the ovp circuit is designed to protect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the max8796/MAX8797 continuously monitor the output for an overvoltage fault. the controller detects an ovp fault if the output voltage exceeds the set vid dac voltage by more than 300mv, subject to a minimum ovp threshold of 0.8v. during pulse-skipping operation (dprslpvr = high), the con- troller initially sets the ovp threshold to a fixed transi- tional ovp threshold (1.8v for imvp-6 or 1.55v for gmch), which is equivalent to 300mv above the maxi- mum vid code allowed. once the output is in regulation (the first on-time is triggered) and the pwrgd blanking time expires, the controller tightens the ovp threshold, tracking the vid target by 300mv. during soft-start and soft-shutdown, the controller also uses the fixed transi- tional ovp threshold. when the ovp circuit detects an overvoltage fault, the max8796/MAX8797 immediately force dl high, pull dh low. this action turns on the synchronous-rectifier mosfets with 100% duty and, in turn, rapidly dis- charges the output filter capacitor and forces the output low. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse will blow. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. ovp protection can be disabled through the no-fault test mode (see the no-fault test mode section). output undervoltage (uvp) protection the output uvp function limits the power loss by dis- abling the regulator if the max8796/MAX8797/max17401 output voltage drops 400mv below the target voltage; the controller activates the shutdown sequence and sets the fault latch. once the controller ramps down to zero, it forces dl and dh low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. uvp protection can be disabled through the no-fault test mode (see the no-fault test mode section). thermal fault protection the max8796/MAX8797/max17401 feature a thermal- fault-protection circuit. when the junction temperature rises above +160c, a thermal sensor sets the fault latch, forces dl low, and pulls dh low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller after the junction temperature cools by 15c. thermal shutdown can be disabled through the no-fault test mode (see the no- fault test mode section). no-fault test mode the latched fault-protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to deter- mine what went wrong. therefore, a no-fault test mode is provided to disable the fault protectionovp, uvp, thermal shutdown, and ton open-circuit fault pro- tection. the no-fault test mode also disables the bst switch, although the switchs body diode provides suffi- cient power for the high-side driver to function properly. additionally, the test mode clears the fault latch if it has been set. the no-fault test mode is entered by forcing 11v to 13v on shdn . mosfet gate drivers the dh and dl drivers are optimized for driving moder- ate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh) source and sink 2.2a, and the low-side gate drivers (dl) source 2.7a and sink 8a. this ensures robust gate drive for high-current applications. the dh high-side mosfet driver is powered by an internal charge-pump boost switch at bst, while the dl synchronous-rectifier driver is powered directly by the 5v bias supply (v dd ). adaptive dead-time circuits monitor the dl and dh dri- vers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates for the adaptive dead-time circuits to work properly; other- wise, the sense circuitry in the max8796/MAX8797/ max17401 interprets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver).
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 41 confidential informa tion?estricted to intel imvp-6 licensees the internal pulldown transistor that drives dl low is robust, with a 0.25 (typ) on-resistance. this helps pre- vent dl from being pulled up due to capacitive coupling from the drain to the gate of the low-side mosfets when the inductor node (lx) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces must guarantee rising lx edges do not pull up the low-side mosfets gate, caus- ing shoot-through currents. the capacitive coupling between lx and dl created by the mosfets gate-to- drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold: typically, adding a 4700pf between dl and power ground (c nl in figure 13), close to the low-side mosfets, greatly reduces coupling. do not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents can be caused by a combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 in series with bst slows down the high-side mosfet turn-on time, elimi- nating the shoot-through currents without degrading the turn-off time (r bst in figure 13). slowing down the high-side mosfet also reduces the lx node rise time, thereby reducing emi and high-frequency coupling responsible for switching noise. quick-pwm design pr ocedur e firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing five factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-con- tributing components. modern notebook cpus gen- erally exhibit i load = i load(max) x 80%. l oad line (voltage positioning): the load line (out- put voltage vs. load slope) dynamically lowers the output voltage in response to the load current, reduc- ing the output capacitance requirement and the processors power dissipation. the intel specification clearly defines the load-line requirement in the power- supply specifications for each processor family. vv c c gs th in rss iss () < ? ? ? ? ? ? bst dh lx input (v in ) c bst c byp v dd (r bst )* (c nl )* n h l dl pgnd (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. n l figure 13. gate-drive circuit
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 42 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees switching frequency: this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target due to rapid improvements in mosfet technology that are mak- ing higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. molded cores are often the best choice, although powdered iron and ferrite cores are inexpensive and can work well at 300khz. the core must be large enough not to satu- rate at the peak inductor current (i peak ): transient response the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time. the worst-case output sag voltage can be determined by: where t off(min) is the minimum off-time (see the electrical characteristics table). the amount of overshoot due to stored inductor energy can be calculated as: current-limit and slew-rate control (time and ilim) time and ilim are used to control the slew rate and cur- rent limit. time regulates to a fixed 2.0v. the max8796/MAX8797/max17401 use the time source current to set the slew rate (dv target /dt). the higher the source current, the faster the output-voltage slew rate: where r time is the sum of resistance values between time and ground. the ilim voltage determines the valley current-sense threshold. when ilim = v cc , the controller uses the preset current-limit threshold22.5mv for imvp-6 designs (max8796/max17401: v3p3 = 3.3v) or 17.5mv for gmch designs (MAX8797 or max8796/ max17401: v3p3 = gnd). in an adjustable design, ilim is connected to a resistive voltage-divider connected between time and ground. the differential voltage between time and ilim sets the current-limit threshold (v limit ), so the valley current-sense threshold is: where the v limit tolerances are defined in the electrical characteristics table. this allows design flexibility since the dcr sense circuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense voltage never exceeds 50mv. keeping v limit between 20mv to 40mv leaves room for future current-limit adjustment. v vv limit time ilim = ? 10 dv dt mv s k r target time /. / . = ? ? ? ? ? ? 12 5 71 5 v il cv soar load max out out () () 2 2 v vt v t sa g ou t s w in of f = () ? ? ? ? ? ? + li l o a d (ma x ) 2 ( m mi n ou t ou t in ou t s w in cv vv t v ) ? ? ? ? ? ? ? () ? ? ? ? ? ? ? 2 t t of f m in () ? ? ? ? ? ? ? ? ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vv f i lir v v in out sw load max out in = ? ? ? ? ? ? ? ? ? ? ? ? ? ()
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 43 confidential informa tion?estricted to intel imvp-6 licensees the minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where: where r sense is the sensing resistor and r csp-csn / r lx-csn is the ratio of resistor-divider with dcr- sensing approach. voltage positioning and loop compensation voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the out- put capacitance and processors power dissipation requirements. the controller uses a transconductance amplifier to set the transient and dc output voltage droop (figure 3) as a function of the load. this adjusta- bility allows flexibility in the selected current-sense resistor value or inductor dcr, and allows smaller cur- rent-sense resistance to be used, reducing the overall power dissipated. steady-state voltage positioning connect a resistor (r fb ) between fb and v out to set the dc steady-state droop (load line) based on the required voltage-positioning slope (r droop ): where the effective current-sense resistance (r sense ) depends on the current-sense method (see the current sense section), and the voltage-positioning amplifiers transconductance (g m(fb) ) is typically 600s as defined in the electrical characteristics table. when the inductors dcr is used as the current-sense element (r sense = r dcr ), the current-sense design should include a thermistor to minimize the temperature dependence of the voltage-positioning slope as shown in figure 1. output capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large-load transients, the output capacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tors esr. the maximum esr to meet ripple require- ments is: where f sw is the switching frequency. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usu- ally selected by esr and voltage rating rather than by capacitance value (this is true of polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: f rc esr eff out = 1 2 f f esr sw r vf l vv v v esr in sw in out out ripple ? () ? ? ? ? ? ? ? ? rr v i esr pcb step load max + () () r r rg fb droop sense m fb = () i v r v dcr r r valley limit sense limit csp csn lx csn == ? ? ii lir valley load max >? ? ? ? ? ? ? () 1 2
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 44 ______________________________________________________________________________________ confidential informa tion?estricted to intel imvp-6 licensees and: where c out is the total output capacitance, r esr is the total esr, r sense is the current-sense resistance (r cm = r cs ), r droop is the voltage-positioning slope, and r pcb is the parasitic board resistance between the out- put capacitors and sense resistors. for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in widespread use at the time of publication have typical esr zero frequencies below 50khz. in the standard gmch application circuit, the esr needed to support a 10mv p-p ripple is 10mv/(10a x 0.3) = 3.3m . two 330f/2.5v panasonic sp (type sx) capacitors in parallel provide 3.0m (max) esr. with a 5m droop and 0.5m pcb resistance, the typical combined esr results in a zero at 28khz. ceramic capacitors have a high-esr zero frequency, but applications with significant voltage positioning can take advantage of their size and low esr. do not put high-value ceramic capacitors directly across the out- put without verifying that the circuit contains enough voltage positioning and series pcb resistance to ensure stability. when only using ceramic output capacitors, output overshoot (v soar ) typically deter- mines the minimum output capacitance requirement. their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con- ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. unstable operation manifests itself in two related but distinctly different ways: double pulsing and feedback loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the i rms requirements can be determined by the fol- lowing equation: the worst-case rms current requirement occurs when operating with v in = 2 x v out . at this point, the above equation simplifies to i rms = 0.5 x i load . for most applications, nontantalum chemistries (ceramic, aluminum, or os-con) are preferred due to their resis- tance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the quick-pwm controller is operated as the second stage of a two-stage power-conversion system, tanta- lum input capacitors are acceptable. in either configu- ration, choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the loss- es at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d 2 pak), and is reasonably priced. make sure that the dl gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate- to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems can occur (see the mosfet gate drivers section). i i v vv v rms load in out in out = ? ? ? ? ? ? ? () rr r r eff esr droop pcb =+ +
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 45 confidential informa tion?estricted to intel imvp-6 licensees mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold volt- age, source inductance, and pcb layout characteris- tics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (2.2a typ). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c x v in 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, you can over design the circuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good-size heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. select a diode that can handle the load current during the dead times. this diode is optional and can be removed if effi- ciency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements of the high-side mosfets. typically, 0.1f ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1f. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified in the mosfets data sheet. for example, assume (2) irf7811w n-channel mosfets are used on the high side. according to the manufacturers data sheet, a sin- gle irf7811w has a maximum gate charge of 24nc (v gs = 5v). using the above equation, the required boost capacitance would be: selecting the closest standard value, this example requires a 0.22f ceramic capacitor. c nc mv f bst = = 22 4 200 02 4 . c nq mv bst gate = 200 ii i i load valley max inductor valley max =+ ? ? ? ? ? ? = () () 2 pd nl sistive v v ir out in max load ds on (r e ) () () =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1 2 pd nhswitching v i f q i cv f in max load sw gs w gate oss in sw () () () = ? ? ? ? ? ? + 2 2 pd nh sistive v v ir out in load ds on (r e ) () = ? ? ? ? ? ? () 2
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 46 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees applications infor mation pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board with their ground terminals flush against one another. follow the max8796 evaluation kit layout and use the following guidelines for good pcb layout: ? high-current path/components: keep the high-cur- rent paths short, especially at the ground terminals. this is essential for stable, jitter-free operation. ? keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcbs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? mosfet drivers: keep the high-current, gate-driver traces (dl, dh, lx, and bst) short and wide to mini- mize trace resistance and inductance. this is essen- tial for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. ? analog control signals: connect all analog grounds to a separate solid copper plane, which connects to the gnd pin of the quick-pwm controller as shown in figures 1, 2, and 14. this includes the v cc bypass capacitor, remote-sense bypass capacitors, and the compensation (ccv) components. ? csp and csn connections for current limiting and voltage positioning must be made using kelvin- sense connections to guarantee the current-sense accuracy. ? route high-speed switching nodes (lx, dh, bst, and dl) away from sensitive analog areas (fb, csp, csn, ccv, etc.). layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper- filled areas. 2 ) mount the controller ic adjacent to the low-side mosfet. the dl gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic). 3 ) group the gate-drive components (bst capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in the standard application circuits. this dia- gram can be viewed as having three separate ground planes: input/output system ground, where all the high-power components go; the power ground plane, where the pgnd pin and v dd bypass capacitor go; and the controllers analog ground plane where sensitive analog components, the analog gnd pin, and v cc bypass capacitor go. the analog gnd plane must meet the pgnd plane only at a single point directly beneath the controller. this star ground point (where the power and analog grounds are connected) should connect to the high-power system ground with a low-impedance connection (short trace or multiple vias) from pgnd to the source of the low-side mosfet. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical.
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller ______________________________________________________________________________________ 47 confidential information?estricted to intel imvp-6 licensees pwrgd v cc v dd shdn on off time gnds r pwrgd 10k r thrm 7.87k ntc2 100k b = 4700 3.3v (vron) r1 8.66k l1 n lo n hi c out lx dh dl bst pgnd csp csn pwr r3 10k ton fb v cc c8 0.1 f 10 1 29 8 9 3 2 4 5 31 23 22 21 25 26 24 11 d1 r10 3.01k r12 2.74k r11 2.00k ntc1 10k b = 3380 thrm vcc_sense vss_sense load-line adjustment : r fb = r droop /(r sense x 600 s) connect v3p3 to agnd for gmch opera tion dcr thermal compensa tion pwr pwr pwr agnd ilim 30 r2 11.4k v alley current limit set by time to ilim v limit = 0.2v x r2/(r2 + r1) slew ra te set by time bias current dv/dt = 12.5mv/ s x 71.5k /(r2 + r1) core output gnd (ep) agnd agnd dprstp 6 dprslpvr 7 clken 13 v3p3 12 ccv 32 agnd agnd agnd pgdin 27 d0 d1 d2 d3 d4 vid inputs agnd 14 15 16 17 18 d5 19 d6 20 vrhot 28 remote-sense inputs remote-sense filters switching frequency (f sw = 1/t sw ): t sw = 16.3pf x (r ton + 6.5k ) r16 10 r15 10 ca tch resistors required when cpu not popula ted agnd r gnd 0 c ccv 100pf c9 1000pf r fb 6.49k 1% r13 10 pwr 33 r4 open 5v bias agnd c in pwr max8796 max17401 agnd agnd pwr r vrhot 10k agnd c csp open c bst 0.1 f r bst 0 r ton 200k agnd c vcc 1.0 f c vdd 1.0 f r vcc 10 c sense 0.1 f agnd c csn open c10 1000pf r14 10 input 7v to 24v 5v bias input figure 14. max8796/max17401 gmch standard application circuit
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller 48 ______________________________________________________________________________________ confidential information?estricted to intel imvp-6 licensees 26 27 25 24 10 9 11 gnds csn csp dprslpvr thrm 12 pwr bst dl pgnd lx stdby d4 12 time 45 6 7 20 21 19 17 16 15 ilim v cc d1 d0 shdn pwrgd MAX8797 fb v dd 3 18 28 8 ccv ton vrhot 23 13 d2 gnd 22 14 d3 dh thin qfn 4mm x 4mm top view pad gnd pin configurations (continued) chip infor mation transistor count: 10,119 process: bicmos package infor mation for the latest package outline information, go to www.maxim-ic.com/packages . package type package code document no. 32 tqfn t3255-3 21-01 40 28 tqfn t2844-1 21-01 39
max8796/MAX8797/max17401 1-phase quick-pwm intel imvp-6/gmch contr oller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 49 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. confidential information?estricted to intel imvp-6 licensees revision history r evi si o n num b e r r evi si o n date d e s cri p t io n pa g es chan g e d 0 11/07 initial release 1 8/08 added max17401 47

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